Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.

Responsive to receiving a table flush command, a first portion of an address mapping table is identified. A first flush operation with respect to a first portion of the address mapping table is performed. Responsive to receiving at least one memory access command, flush operations for a subsequent portion of the address mapping table is suspended. At least one memory access operation specified by the at least one memory access command is performed. A second flush operation with respect to the subsequent portion of the address mapping table is performed.

Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

A method and apparatus for a database management architecture on an SSD. A list of tables is stored in the SSD, and records of a table are stored across multiple FIMs of the SSD such that a group of records may be read in parallel by concurrently reading from multiple FIMs. The records of the table are stored on jumboblocks, organized in an unordered fashion as a linked list. New records are added to the end of the linked list. Records having gaps resulting from data modification or bad portions of an NVM die are re-organized via garbage collection when the gap memory size reaches about 20% of table memory size.

A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

One or more units of decompressed data of a plurality of units of decompressed data is written to a target location for subsequent writing to memory. The plurality of units of decompressed data includes a plurality of symbol outputs and has associated therewith a plurality of decompression headers. A determination is made that the subsequent writing to memory of at least a portion of another unit of decompressed data to be written to the target location is to be stalled. A symbol start position of the other unit of decompressed data and a decompression header of a selected unit of the one or more units of decompressed data written to the target location are provided to a component of the computing environment. The decompression header is used for the subsequent writing of the other unit of decompressed data to memory.

A method and an apparatus for processing Bitmap data are provided by the embodiments of the present disclosure. The method for processing Bitmap data includes: dividing a Bitmap region in a disk into a plurality of partitions in advance and setting an update region in the disk; obtaining a respective amount of dirty data corresponding to each of the plurality of partitions in memory in response to a condition for writing back to the disk being satisfied; finding multiple second partitions with an amount of dirty data satisfying to be merged into the update region from the plurality of partitions according to the respective amount of dirty data corresponding to each of the plurality of partitions; and recording dirty data corresponding to the multiple second partitions in the memory into the update region in the disk through one or more I/O operations after merging.

The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

Cache coherency of a global address space of a cache can be maintained with one or more tier control units (TCUs). The global address space of the cache may be shared by multiple domains. Domains may include multiple controllers and a local interconnect operatively coupling the controllers to the cache. The local interconnect of each domain may maintain a cache coherency of a local address space of the cache shared by the controllers of the domain. The one or more TCUs may be operatively coupled to the local interconnects of the domains to maintain the cache coherency of the global address space.

A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.