Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

A combined on-package and off-package memory system uses a custom base-layer within which are fabricated one or more dedicated interfaces to off-package memories. An on-package processor and on-package memories are also directly coupled to the custom base-layer. The custom base-layer includes memory management logic between the processor and memories (both off and on package) to steer requests. The memories are exposed as a combined memory space having greater bandwidth and capacity compared with either the off-package memories or the on-package memories alone. The memory management logic services requests while maintaining quality of service (QoS) to satisfy bandwidth requirements for each allocation. An allocation may include any combination of the on and/or off package memories. The memory management logic also manages data migration between the on and off package memories.

A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

A method for block addressing is provided. The method includes moving content of a data block referenced by a logical block address (LBA) from a first physical block corresponding to a first physical block address (PBA) to a second physical block corresponding to a second PBA, wherein prior to the moving a logical map maps the LBA to a middle block address (MBA) and a middle map maps the MBA to the first PBA and in response to the moving, updating the middle map to map the MBA to the second PBA instead of the first PBA.

A technique performs data reduction on host data of a write request during ingest under certain circumstances. Therein, raw host data of a write request is placed from the host into a data cache. Further, a data reducing ingest operation is performed that reduces the raw host data from the data cache into reduced host data (e.g., via deduplication, compression, combinations thereof, etc.). After completion of the data reducing ingest operation, performing a late-binding operation is performed that updates a mapper with ability to access the reduced host data from secondary storage. Such ingest-time data reduction may be enabled/disabled (e.g., turned on or off) per input/output (I/O) operation (e.g., used only for relatively large asynchronous I/O operations) and/or activated in situations in which the ingest bandwidth is becoming a bottleneck.

A method, computer program product, and computing system for receiving a flush request for a metadata page stored in a storage array of a multi-node storage system. The flush request may be queued on a flush request lock queue on at least one node of the multi-node storage system. One or more flush requests may be processed, via multiple nodes of the multi-node storage system, on the metadata page based upon, at least in part, the flush request lock queue.

Methods, systems, and computer-readable storage media for determining that a transaction of a plurality of transactions performed in at least a portion of a system includes a delete operation, the plurality of transactions being managed by a secondary transaction manager and including a subset of all transactions performed in the system, in response to the delete operation, inserting a clean-up entry in the secondary transaction manager, attaching the clean-up entry to a subsequent transaction in order to determine and assign a time to the cleanup-entry that is used to subsequently trigger garbage collection, and selectively comparing the time to a most-recently-reported minimum read timestamp that is periodically reported to the secondary transaction manager from a primary transaction manager of the system, wherein the clean-up entry is executed in response to determining that the time is less than the most-recently-reported minimum read timestamp.

An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

An apparatus comprises a processing device configured to monitor a storage cache storing a plurality of cache pages to determine whether the storage cache reaches one or more designated conditions and to determine cache replacement scores for at least a subset of the cache pages, the cache replacement scores being determined based at least in part on input-output access types for data stored in the cache pages. The processing device is also configured to select, responsive to determining that the storage cache has reached at least one of the one or more designated conditions, at least one of the cache pages to move from the storage cache to a storage device based at least in part on the determined cache replacement scores. The processing device is further configured to move the selected at least one of the plurality of cache pages from the storage cache to the storage device.

Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.