G06F2212/173

FLASH EMULATED EEPROM WRAPPER
20170220252 · 2017-08-03 ·

This relates to a file system, and more particularly to, a file system compatible with multiple types of non-volatile memory for safety-critical embedded systems, such as an Electronic Control Unit (ECU) of an automobile. Some examples of the disclosure include an ECU having RAM and non-volatile memory managed by a file system. In some examples, non-volatile memory can include a flash-emulated EEPROM (FEE) device. A wrapper function can provide an interface between a file system and one or more hardware devices, allowing the file system and application code to be compatible with multiple kinds of hardware.

MEMORY POOLING BETWEEN SELECTED MEMORY RESOURCES
20210406087 · 2021-12-30 ·

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

ACCESS CONTROL MECHANISM IN CACHE COHERENT INTEGRATED CIRCUIT
20220194366 · 2022-06-23 ·

Disclosed embodiments provide systems and methods that can be used as part of or in combination with autonomous navigation, autonomous driving, or driver assist technology features. As opposed to fully autonomous driving, driver assist technology may refer to any suitable technology to assist drivers in the navigation or control of their vehicles. In various embodiments, the system may include one or more cameras mountable in a vehicle and an associated processor that monitors the environment of the vehicle. In further embodiments, additional types of sensors can be mounted in the vehicle and can be used in the autonomous navigation or driver assist systems. These systems and methods may include the use of a shared cache that is shared by a group of processing units to improve analysis of images captured by the one or more cameras.

Electronic control unit for vehicle and method of writing data
11360698 · 2022-06-14 · ·

An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.

Memory device with cryptographic kill switch
11726923 · 2023-08-15 · ·

Devices and methods for preventing unauthorized access to memory devices are disclosed. A one-time programmable (OTP) memory is included in both a memory device and a processing device. The OTP memories store encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

VEHICLE DEVICE AND VEHICLE DEVICE CONTROL METHOD
20220024466 · 2022-01-27 ·

A vehicle device includes a plurality of CPU modules, a plurality of cache memories respectively provided for the plurality of CPU modules, a specifying unit configured to specify a shared region shared by the plurality of CPU modules, and a region arrangement unit configured to arrange the shared region specified by the specifying unit in a main memory.

Media type selection

Systems, apparatuses, and methods related to media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and can write data to the memory media types. Data inputs can be written (e.g., stored) in a particular type of memory media based on characteristics (e.g., source, attributes, and/or information etc. included in the data). For instance, selection of memory media can be based on characteristics of the memory media type and the attributes of the data input. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, data from at least one of a plurality of sensors, identifying one or more attributes of the data; and selecting, based at least in part on the one or more attributes of the data, one or more of the memory media types to write the data to.

Reconfigurable memory mapped peripheral registers

A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Memory pooling between selected memory resources

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.