A method of caching large data objects of greater than 1 GB, comprising: populating a sharded cache with large data objects backfilled from a data store; servicing large data object requests from a plurality of worker nodes via the sharded cache, comprising deterministically addressing objects within the sharded cache; and if a number of requests for an object within a time exceeds a threshold: after receiving a request from a worker node for the object, sending the worker node a redirect message directed to a hot cache, wherein the hot cache is to backfill from a hot cache backfill, and wherein the hot cache backfill is to backfill from the sharded cache.

Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

A method is described for calibrating a vehicle control unit, a data exchange taking place via a voltage supply line connected to the vehicle control unit, as well as a vehicle control unit, which is configured to carry out a data exchange for calibrating the vehicle control unit via a voltage supply line connected to the vehicle control unit with the aid of a communication signal (powerline communication) modulated to the supply voltage. A corresponding measuring and calibration system is also described.

A computing system comprises at least one processing unit, at least one memory controller in communication with the processing unit, and a main memory in communication with the processing unit through the memory controller. A memory hierarchy of the computing system includes at least one cache, the memory controller, and the main memory. The memory hierarchy is divided into a plurality of memory pools. The main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits. Each rank has a set of memory devices comprising one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads execute on the processing unit, and are assigned to the memory pools based on one or more memory partitioning techniques, including bank partitioning, rank partitioning, or memory controller partitioning.

Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

A communication method applied to a computer system that includes a first subsystem and a second subsystem. A safety level of the first subsystem is higher than a safety level of the second subsystem. The first subsystem includes a memory access checker. The method includes the memory access checker receives a memory access request from a memory access initiator, determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and allows the memory access initiator to access the memory address when the safety level of the memory matches the safety level of the memory access initiator.

A method for disaggregated cache memory for efficiency in distributed databases includes receiving, from a user device, a first query requesting first data be written to a distributed database. The distributed database includes a plurality of nodes each controlling writes to a respective portion of the distributed database and a distributed cache pool caching a subset of the distributed database independently from the plurality of nodes. The method includes writing, using one of the plurality of nodes, the first data to the distributed database. The method also includes receiving, from the user device, a second query requesting second data be read from the distributed database. The method further includes retrieving, from the distributed cache pool, the second data. The method includes providing, to the user device, the second data retrieved from the distributed cache pool.

A shared data management system configured to receive frames comprising data from one or more producer devices and to transmit reconstructed frames to one or more consumer devices, a producer device and a consumer device being connected to the shared data management system by way of a communication network using a communication protocol. The shared data management system comprises a memory system having one or more memories. The shared data management system advantageously comprises a central controller configured to store at least some of the data encapsulated in a frame received from a producer device in a target memory area of the memory system, the central controller being configured to compute, for each datum to be stored, the address of the target memory based on an index associated with the datum in the received frame.

A memory device stores data for a host device. In one approach, a method includes: selecting, by the memory device, a first mode of operation for a host interface that implements a communication protocol for communications between the memory device and the host device. The host interface is configured to implement the communication protocol using a mode selected by the memory device from one of several available modes. In response to selecting the first mode, resources of the memory device are configured to customize the host interface for operation in the first mode.