A disclosed stream memory management circuit includes a first memory controller circuit for accessing a first memory of a first type. A second memory controller circuit is provided for accessing a second memory of a second type different from the first type. An access circuit is coupled to the first and second memory controller circuits for inputting and outputting streaming data. An allocation circuit is coupled to the access circuit, the allocation circuit configured and arranged to select either the first memory or the second memory for allocation of storage for the streaming data in response to attributes associated with the streaming data. A de-allocation circuit is coupled to the access circuit for de-allocating storage assigned to the streaming data from the first and second memories.

The present disclosure proposes a method used by a receiver for facilitating de-rate matching of bits of symbols formed after a rate matching procedure from a transmitter, wherein the transmitter selected Z bits from channel-coded bits, and then generated E bits by concatenation of the Z bits and their copies for the rate matching procedure. The method comprises: demodulating the symbols to obtain E soft bits corresponding to the E bits; zeroing values at Z consecutive locations of a memory, wherein the Z consecutive locations correspond to bit positions of the Z bits; writing the E soft bits into a buffer device; for each soft bit of the E soft bits in the buffer device, directly adding value of the soft bit and value from a location of the Z consecutive locations and storing result of the addition back into the location, wherein a bit in the E bits corresponding to the soft bit is a bit in the Z bits corresponding to the location or a copy of the bit in the Z bits; and restoring the Z bits from the final results at the Z consecutive locations. The method facilitates the de-rate matching by reducing its memory usage and processing latency.

A time de-interleaving circuit is located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. The time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the plurality of data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the plurality of common units in the memory. The second address sequence is a reverse sequence of the first address sequence.

As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions.

A computer-implemented method for memory management can include identifying a set of one or more memory blocks of virtual memory to be allocated for storage of a content into a plurality of memory banks that subdivide physical memory. The method can include storing the content in the set of one or more memory blocks of virtual memory. The method can include assigning an identifier to the set of one or more memory blocks of virtual memory that store the content. The method can include outputting the identifier for the set of one or more memory blocks of virtual memory. Various other methods, systems, and computer-readable media are also disclosed.