An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys.

Apparatuses, systems, methods, and computer program products are disclosed for providing a memory device with volatile and non-volatile media. A volatile memory medium is on a circuit board configured to be installed on a memory bus of a processor. A non-volatile memory medium is on the same circuit board. A mapping module is configured to selectively store data in either the volatile memory medium or the non-volatile memory medium. The data is provided by way of one or more commands from the processor.

Techniques for efficiently purging non-active blocks in an NVM region of an NVM device using virtblocks are provided. In one set of embodiments, a host system can maintain, in the NVM device, a pointer entry (i.e., virtblock entry) for each allocated data block of the NVM region, where page table entries of the NVM region that refer to the allocated data block include pointers to the pointer entry, and where the pointer entry includes a pointer to the allocated data block. The host system can further determine that a subset of the allocated data blocks of the NVM region are non-active blocks and can purge the non-active blocks from the NVM device to a mass storage device, where the purging comprises updating the pointer entry for each non-active block to point to a storage location of the non-active block on the mass storage device.

In one embodiment, sequential write stream management is employed to improve the sequential nature of write data placed in a storage such as a solid state drive, notwithstanding intermingling of write commands from various sequential and nonsequential streams from multiple processor nodes in a system. In one embodiment, write data from an identified sequential write stream is placed in a storage area assigned to that particular identified sequential write stream. In another aspect, detected sequential write streams are identified as a function of write velocity of the detected stream. Other aspects are described herein.

A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.

The present invention relates to a security module and to a corresponding method for operating the security module for realizing a secure memory management. The subject matter according to the invention takes into account existing hardware components, for example a smart card, and can thus be integrated into existing smart cards with particularly little technical effort. The secure memory management prevents attacks against memory segments of the data memory.

A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.

A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.