A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Technologies disclosed herein provide mitigations against warm boot attacks on memory modules. For instance, in one embodiment, a non-volatile dual in-line memory module (NVDIMM) in a host computing system may detect a transition from a low-power state to a full-power state, receive a nonce value from a processor of the host computing system after the transition, verify the nonce value, and allow access to data stored on the NVDIMM based on successful verification of the nonce value. In another embodiment, an NVDIMM may be locked in response to detecting a transition from a high-power state to a low-power state in a host computing system. After a transition from the low-power state to the full-power state, the NVDIMM may obtain one or more passphrases, verify the one or more passphrases, and allow access to data stored on the NVDIMM based on successful verification of the one or more passphrases.

According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.

A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to generate a scrambler seed and a logical block address (LBA) for a block of write data received via the communication interface, scramble the block of data using the scrambler seed, encrypt the scrambler seed and the LBA using an encryption key, initiate writing a scrambled block of data and encrypted LBA and scrambler seed to the memory array, and change the encryption key in response to an erase command received via the communication interface.

Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access rules defining permissible access to the identified memory addresses that depends on the value of one or more registers stored in the memory system. In some examples, the value of the registers (e.g., a Platform Configuration Register) may depend on a state of a computing device in which the memory system is installed.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.

In a method for managing a storage device in a storage system, a client may send, based on an obtained start address that is of a queue of an NVMe storage device and to which an access request points and an obtained logical address that is of the NVMe storage device and to which the access request points, a remote direct memory access command to a storage node in which the NVMe storage device is located.