An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.

According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A method for reprogramming data, performed by a processing unit, is disclosed to include at least the following steps. After a page of data has failed to be programmed into a first block of a storage unit, it is determined whether the failed page is an upper page or a first lower page. When the failed page is an upper page, a host page number associated with a second lower page of a wordline including at least the failed page is obtained, a second block is selected, and an access interface is directed to reprogram data from the second lower page to the upper page into the second block.

An electronic device with volatile memory repeatedly compares an amount of free volatile memory to a first predetermined threshold level of free volatile memory. When the device determines that the amount of free volatile memory is less than the first predetermined threshold level, the device deallocates volatile memory by terminating one or more processes based on predetermined priority levels of the one or more processes.

A memory system having non-volatile memory backup with high-speed programming capability. The non-volatile memory, such as flash memory, is pre-aged before first use in a host system. Pre-aging includes execution of a plurality of dummy program and erase cycles as part of the memory system or before assembly as part of the memory system. The memory system can include an NVDIMM having flash memory backup. The pre-aged flash memory programs a page of data in a shorter period of time relative to new flash memory. Fewer flash memory chips are needed in the memory system relative to memory systems using new flash memory chips, thereby reducing cost of the memory system. The NVDIMM may be used to backup data from a volatile memory device such as a DRAM. Programming times may be tracked after each dummy program/erase cycle, and for each programmable page of a memory block.

A memory system which includes a memory pool having a plurality of memory units and a controller suitable for controlling the plurality of memory units, wherein the controller includes a translation unit suitable for translating a system address into a local address within the memory pool, a threshold decision unit suitable for dynamically changing a threshold based on an a number of accesses to each local address for data within the memory pool, a data attribute determination unit suitable for determining an attribute of data associated with the translated local address based on the threshold and the number of accesses to the translated local address, and a data input/output unit suitable for controlling a memory unit associated with a new local address among the plurality memory units based on the attribute of the data.

A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

Apparatus, systems, and methods to implement polarity based data transfer function on a write data unit are described. The transfer function takes into account certain data values that are common, and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values.