An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.

A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1.sup.st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the i.sup.th time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i1).sup.th time.

A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.

The present disclosure discloses a processor security checking method, system and checking device. The processor security checking method includes: acquiring recording information of data read and write operations between a processor and a peripheral device, where the data read and write operation is a data read and write operation initiated by the processor or a data read and write operation initiated by the peripheral; and determining whether the processor is secure according to the recording information of the data read and write operation and an analysis result on the data read and write operation by the checking device. The embodiments of the present disclosure may detect hardware vulnerabilities and improve the security of hardware usage.

A system and method for efficient write through processing of Input/Output (I/O) requests are provided. One example of the illustrative method includes receiving a first write request to a first row, while processing the first write request, receiving a subsequent write request to the first row, and then caching the subsequent write request for processing until the first write request is completed.

An apparatus includes a plurality of root ports serving as roots of bus connection of a plurality of devices including boot devices from which legacy boot is executed to boot an operating system (OS). A processor included in the apparatus identifies a single boot device among the boot devices and a single root port connected to the single boot device, and allocates, as memory addresses to be used for memory mapped input and output, memory addresses with a bit width available during the legacy boot to devices connected to the identified single root port. The processor determines whether the memory addresses have been allocated to all devices connected to the single root port, and executes the legacy boot to boot the OS from the single boot device when the memory addresses have been allocated to all the devices connected to the single root port.

Disclosed herein is a persistent memory (PMEM)-based distributed memory object system, referred to as the PMEM DMO system, that provides affordable means of integrating low-latency PMEM spaces with other devices, including servers that do not directly support PMEM. One embodiment comprises providing a cluster of servers with PMEM storage (PMEM servers) and connecting the PMEM servers to a plurality of applications servers using a low-latency network, such as a remote direct memory access; background processes on each of the application servers are tasked to perform input/output operations for the application servers to locally materialize objects from and synchronize/persist objects to the remote PMEM spaces on the PMEM servers. Data materialized from the PMEM servers is stored to the local cache of the application server for use. Also disclosed are data eviction policies for clearing the local cache of the application servers to make space for new data read.

Disclosed herein is an apparatus and method for a key value store snapshot for a distributed memory object system. In one embodiment, a method includes forming a system cluster comprising a plurality of nodes, wherein each node includes a memory, a processor and a network interface to send and receive messages and data; creating a plurality of sharable memory spaces having partitioned data, wherein each space is a distributed memory object having a compute node, wherein the sharable memory spaces are at least one of persistent memory or DRAM cache; storing data in persistent memory, the data having a generation tag created from a generation counter and a doubly linked list having a current view and a snapshot view, the data further being stored in either a root or a persisted row; creating a snapshot comprising a consistent point-in-time view of key value contents within a node and incrementing the generation counter; copying the snapshot to a second node; regenerating an index for the key value contents within the node; and logging updates since the snap was applied to update copied data in the second node.

An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.