A device implementing purgeable memory mapped files includes at least one processor configured to receive a first request to store a first data object in volatile memory in association with a copy of the first data object stored in non-volatile memory, the first request indicating to lock the copy in the non-volatile memory. The processor is further configured to provide for storing the first data object in the volatile memory, and lock the copy stored in the non-volatile memory. The processor is further configured to receive a second request associated with clearing a portion of the non-volatile memory, provide an indication that a second data object is available for deletion from the non-volatile memory when the first data object is locked, and provide an indication that the first data object is available for deletion from the non-volatile memory when the first data object has been unlocked.

In accordance with an embodiment, described herein is a system and method for improving performance within a multidimensional database computing environment. A multidimensional database, utilizing a block storage option, performs numerous input/output (I/O) operations when executing calculations. To separate I/O operations from calculations, a background task queue is created to identify data blocks requiring I/O. The background task queue is utilized by background writer threads to execute the I/O operations in parallel with calculations.

Direct access to host memory for guests is disclosed. For example, a system includes a processor, a host memory, a filesystem daemon, a guest including a storage controller, and a filesystem queue accessible to the filesystem daemon and the storage controller. The storage controller receives a file retrieval request associated with a file stored in the host memory and forwards the file retrieval request to the filesystem daemon by adding the file retrieval request to the filesystem queue. The filesystem daemon retrieves the file retrieval request from the filesystem queue, determines a host memory address (HMA) associated with the file, and causes the HMA to be mapped to a guest memory address (GMA). The guest accesses the file in the host memory with the GMA, and later terminates access to the file, where the filesystem daemon is then configured cause the GMA to be unmapped.

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

A storage device includes a nonvolatile memory device, a random access memory that includes a first region and a second region, and a controller that is configured to use the first region of the random access memory as a journal memory for a journal indicating modification of data of the second region, expose a user region of the nonvolatile memory device to an external host device as a first access region of a block unit, and expose the second region of the random access memory to the external host device as both a second access region of the block unit and a third access region of a byte unit.

Direct access to host memory for guests is disclosed. For example, a system includes a processor, a host memory, a filesystem daemon, a guest including a storage controller, and a filesystem queue accessible to the filesystem daemon and the storage controller. The storage controller receives a file retrieval request associated with a file stored in the host memory and forwards the file retrieval request to the filesystem daemon by adding the file retrieval request to the filesystem queue. The filesystem daemon retrieves the file retrieval request from the filesystem queue, determines a host memory address (HMA) associated with the file, and causes the HMA to be mapped to a guest memory address (GMA). The guest accesses the file in the host memory with the GMA, and later terminates access to the file, where the filesystem daemon is then configured cause the GMA to be unmapped.

Examples described herein provide for memory access protection in programmable logic devices. In an example, an integrated circuit includes a programmable logic region, control logic, an interconnect, and a memory controller. The control logic is communicatively coupled to the programmable logic region. The control logic is configurable to generate one or more transaction attributes of a memory transaction request, and the memory transaction request is communicated from the programmable logic region. The interconnect is communicatively coupled to the control logic. The interconnect is operable to communicate the memory transaction request therethrough. The memory controller is communicatively coupled to the interconnect. The memory controller is operable to receive the memory transaction request. The memory controller is configurable to determine whether the memory transaction request is permitted based on the one or more transaction attributes.

A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.