Storage management techniques involve: acquiring target data in a target storage page in a memory; determining, based on the target data, check information and identification information associated with the target data, the check information being used to verify whether the target data is correct and the identification information being used to identify the target data; and determining, based on the identification information, storage information associated with the target data and the check information, the storage information indicating whether to store the target data and the check information to a persistent storage device. Therefore, the processing efficiency can be improved, and the input/output (I/O) performance can be improved.

A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving a request to access data via an input/output (I/O) device, determining whether the data is stored in a non-persistent memory device or a persistent memory device, and redirecting the request to access the data to logic circuitry in response to determining that the data is stored in the persistent memory device.

A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

A controller of a non-volatile, dual, in-line memory modules (NVDIMM). A NVDIMM is configured to predict thermal events associated with save and restore operations prior to starting the save or restore operation. The controller of the NVDIMM includes a thermal event prediction circuit to predict whether a thermal event will occur in response to a request to perform a save or restore operation, and to cause the controller to perform an action in response to a determination that a thermal event is likely to occur. To predict the thermal event, the controller may be configured to predict a peak temperature of the save or restore operation based on a predicted temperature increase from an initial or starting temperature. The predicted temperature increase may be based on a rate of temperature change during the save or restore operation and a duration of the save or restore operation.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.

Methods, systems, and devices for quality-of-service information for a multi-memory system are described. An interface controller may receive a first command from a host device during a set of clock cycles. The first command may be received over a command bus that includes a pin, such as a command select pin configured for double data rate signaling. The interface controller may decode the first command based on a state of the command select pin during at least one clock cycle of the set of clock cycles. And the interface controller may determine quality-of-service information for a second command based on decoding the first command and on information, such as a plurality of bits, included in the first command.

In at least one implementation, technology disclosed herein provides a method including generating a plurality of shares of an encryption key such that a combination of shares having a cardinality above a threshold cardinality is sufficient to retrieve data encrypted with the encryption key, distributing the plurality of shares among a plurality of devices, the plurality of devices including one or more disc drive cartridges and one or more printed circuit board assemblies (PCBAs) configured to host one or more of the disc drive cartridges, receiving one or more of the plurality of shares from the plurality of devices, and in response to determining that cardinality of the received one or more of the plurality of shares is above the threshold cardinality, retrieving the data encrypted with the key.