A method, computer program product, and computing system for assigning a plurality of unique sequential identifiers to a plurality of tablets in a cache memory system. One or more metadata deltas associated with a metadata page stored in a storage array may be written to the plurality of tablets in the cache memory system. Each metadata delta stored in at least one tablet of the plurality of tablets may be written to the metadata page stored in the storage array, thus defining one or more destage tablets. A largest unique sequential identifier from the plurality of unique sequential identifiers assigned to the one or more destage tablets, may be written to the storage array, thus defining a current tablet identifier for the metadata page.

A method, computer program product, and computer system for controlling, by a computing device, access to a non-volatile memory using a non-volatile lock as a reader of the non-volatile memory. Metadata (MD) non-volatile memory commits may be throttled until capacity of the non-volatile memory is at a threshold capacity.

A data processing method and a corresponding system are provided. The method is implemented by a processor and includes: obtaining a to-be-processed I/O request, where the to-be-processed I/O request may include a first address, and the first address is a logical address of to-be-read, to-be-written, or to-be-erased data in a target SSD; performing address translation on the to-be-processed I/O request based on an FTL mapping table, to translate the first address into a second address, where the second address is used to indicate a physical address of the to-be-read, to-be-written, or to-be-erased data in the target SSD, and the FTL mapping table may be used to record a translation relationship between physical addresses and logical addresses in the n SSDs; sending a to-be-processed I/O request obtained after address translation is performed; and after a sleep duration is preset, querying a processing result of the to-be-processed I/O request.

Methods, non-transitory machine readable media, and computing devices that use extended physical region page (PRP) lists to improve storage device performance are disclosed. With this technology, a PRP list is generated that includes pointers retrieved from a scatter/gather list (SGL) for memory buffers representing data segments associated with a storage operation. The PRP list is extended to include a pointer to an allocated memory page configured to store metadata segments represented by other memory buffers referenced by other pointers in the SGL. A command request that includes the extended PRP list is submitted to a storage device for execution of the storage operation. With this technology, storage operations are advantageously enabled for non-volatile memory express (NVMe) solid-state drive (SSDs), for example, that do not support SGL transfers.

Aspects of a storage device are provided which reduce write amplification by minimizing data flushes from cache to SLC blocks during RMW operations. A memory of the storage device includes a first memory location of one or more single-level cells and a second memory location of one or more multiple-level cells. A controller of the storage device receives first data associated with a first range of logical addresses and second data associated with a second range of logical addresses. During a RMW operation of the first data, the controller determines whether the first range overlaps with the second range, and stores or flushes the second data in the first memory location when an overlap is determined. The controller stores or writes the second data in the second memory location when an overlap is not determined. Accordingly, data flushing to the single-level cells is minimized when no overlap is determined.

Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.

A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.

Described are examples for storing, in a first zone cache, one or more logical blocks (LBs) corresponding to a data chunk, writing, for each LB in the data chunk, a cache element of a cache entry that points to the LB in the first zone cache, where the cache entry includes multiple cache elements corresponding to the multiple LBs of the data chunk, writing, for the cache entry, a table entry in a mapping table that points to the cache entry, and when a storage policy is triggered for the cache entry, writing the multiple LBs, pointed to by each cache element of the cache entry, as contiguous LBs in an isolation block for the data chunk in a second zone stream, and updating the table entry to point to the isolation block in the second zone stream.