A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.

A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends an update data chunk obtained from to-be-written data to a corresponding storage node. The storage node does not directly update, based on the received update data chunk, a data block stored in a storage device of the storage node, but store the update data chunk into a non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node for backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

A processor may boot a system. The processor may determine a type of operation of data based on an application tag. The processor may analyze at least one specific table for the application tag. The processor may perform an operation associated with the application tag.

Data base performance is improved using write-behind optimization of covering cache. Non-volatile memory data cache includes a full copy of stored data file(s). Data cache and storage writes, checkpoints, and recovery may be decoupled (e.g., with separate writes, checkpoints and recoveries). A covering data cache supports improved performance by supporting database operation during storage delays or outages and/or by supporting reduced I/O operations using aggregate writes of contiguous data pages (e.g., clean and dirty pages) to stored data file(s). Aggregate writes reduce data file fragmentation and reduce the cost of snapshots. Performing write-behind operations in a background process with optimistic concurrency control may support improved database performance, for example, by not interfering with write operations to data cache. Data cache may store (e.g., in metadata) data cache checkpoint information and storage checkpoint information. A stored data file may store storage checkpoint information (e.g., in a file header).

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

The present disclosure includes apparatuses and methods related to a memory protocol with programmable buffer and cache size. An example apparatus can program a resister to define a size of a buffer in memory, store data in the buffer in a first portion of the memory defined by the register, and store data in a cache in a second portion of the memory.

A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

A method, computer program product, and computing system for receiving, via a storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to the storage processor, where the write request may be received from a host. The data portion may be written to a persistent memory write cache within the storage array enclosure.

A method, computer program product, and computing system for receiving, at a local node, a request to buffer data on a remote persistent cache memory system of a remote node. A target memory address within the remote persistent cache memory system may be sent from the local node via a remote procedure call (RPC). The data may be sent from the local node to the target memory address within the remote persistent cache memory system via a remote direct memory access (RDMA) command.