Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.

A method for depopulating data from cache includes receiving a command to depopulate the cache of selected data. The command has an application identifier as a parameter. The application identifier is associated with an application that previously accessed the data. The method searches the cache for data elements that are marked with the application identifier and removes the data elements from the cache. In certain embodiments, the data elements are marked with a first application identifier associated with an application that staged the data elements into the cache, and a second application identifier associated with an application that last accessed the data elements. In certain embodiments, removing the data elements from the cache comprises only removing the data elements from the cache if the application identifier matches one or more of the first application identifier and the second application identifier. A corresponding system and computer program product are also disclosed.

Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.

A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method also maintains, for the data element, a read access count that is incremented each time a data element is read in the cache. The method removes the data element from the higher performance portion of the cache in accordance with a cache demotion algorithm. If the write access count is below a first threshold and the read access count is above a second threshold, the method places the data element in the lower performance portion. A corresponding system and computer program product are also disclosed.

The devices within an inter-device processing system maintain data coherency in the last level caches of the system as a cache line of data is shared between the devices by utilizing a directory in one of the devices that tracks the coherency protocol states of the memory addresses in the last level caches of the system.

A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The method maintains a plurality of favored LRU lists and a non-favored LRU list for the higher and lower performance portions of the cache memory. Each favored LRU list contains entries associated with the favored storage elements that have the same unique residency multiplier. The non-favored LRU list includes entries associated with the non-favored storage elements. The method demotes a selected favored or non-favored storage element from the higher and lower performance portions of the cache memory according to a cache demotion policy that provides a preference to favored storage elements over non-favored storage elements based on a computed cache life expectancy, residency time, and the unique residency multiplier. A corresponding storage controller and computer program product are also disclosed.

A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The favored storage elements are retained in the cache memory longer than the non-favored storage elements. The method maintains a first favored LRU list and a first non-favored LRU list, associated with the favored and non-favored storage elements stored within the higher performance portion of the cache. The method selects a favored or non-favored storage element to be demoted from the higher performance portion of the cache memory according to life expectancy and residency of the oldest favored and non-favored storage elements in the first LRU lists. The method demotes the selected from the higher performance portion of the cache to the lower performance portion of the cache, or to the data storage devices, according to a cache demotion policy. A corresponding storage controller and computer program product are also disclosed.

A computer based system and method for managing memory resources in a computing system may include, using a computer processor, receiving, from a computing system, a memory transaction request originating from a process executing on the computing system. Translation of a memory address associated with the request, or provisioning of memory for a translated address, may be determined based on various memory-transactions-related metadata—such as the service level of the process; the service level of other processes; access patterns of memory resources; a prediction of future memory requests of a process, and the like.

A storage control device includes: an auxiliary cache memory that is a nonvolatile memory; a volatile memory; and a processor configured to execute a saving control process after a predetermined failure occurs, the saving control process being configured to (a) cause a writing control process to stop writing of data stored in the auxiliary cache memory to the storage medium, (b) secure, in the auxiliary cache memory, a storage region for storing the management information of the volatile memory, (c) generate a copy of management information of the volatile memory in the storage region, and (d) cause the writing control process to execute control to write first data stored in the volatile memory to the auxiliary cache memory or the storage medium based on the management information of the auxiliary cache memory.

The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.