In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level. The memory management system may assign an initial priority level to a memory page in a page priority list. The memory management system may change the memory page to a target priority level in the page priority list after a protection period has expired.

This document describes profiling cache replacement. Profiling cache replacement is a technique for managing data migration between a main memory and a cache memory to improve overall system performance. Unlike conventional cache replacement techniques, profiling cache replacement employs a profiler to maintain counters that count memory requests for access to not only the pages maintained in the cache memory, but also the pages maintained in the main memory. Based on the information collected by the profiler (e.g., about memory access requests), a mover moves pages between the main and cache memories. By way of example, the mover can swap highly-requested pages of the main memory, such as a most-requested page of the main memory, with little-requested pages of the cache memory, such as a least-requested page of the cache memory. The mover can do so, for instance, when the counters indicate that the number of page access requests for highly-requested pages of the main memory is greater than the number of page access requests for little-requested pages of the cache memory. So as not to impede the operations of memory users (e.g., client applications), the mover performs the page swapping in the background. To do so, the mover is limited to swapping pages at predetermined time intervals, such as once every microsecond (μs).

An electronic device is provided. The electronic device includes a processor, a volatile memory, and a storage. The processor is configured to, in response to a request for data included in a file, identify information of the file and a type of the request, configure a flag for the request if the file is determined to correspond to at least one in a list of a designated information table, identify, based on the flag, mapping information of a specific region, which includes a logical address of the data, in mapping information for mapping of logical addresses and physical addresses for the non-volatile memory of the storage, acquire, in response to the mapping information of the specific region existing in the volatile memory, a physical address of the non-volatile memory mapped to the logical address of the data, and transmit the request, including the acquired physical address of the non-volatile memory, to the storage.

A computer system includes a processor and a processing circuit. The processor has an embedded memory. The processing circuit is arranged to perform a write operation for writing a first write data into the embedded memory included in the processor. The processor is arranged to load and execute a program code to perform a read operation for reading the first write data from the embedded memory included in the processor.

Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.

An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to allocate a memory location for a parameter passed to a callee. The caller is a module that includes a function call to the callee and the callee is a function. The method may include inserting instructions in the callee to allocate a home memory location for the parameter in response to determining that the caller is not configured to allocate a memory location for the parameter. In addition, the method may include inserting instructions in the callee to set the memory location as a home location for the parameter in response to determining that the caller is configured to allocate a memory location for the parameter.

A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

The disclosure relates to filtering snoops in coherent multiprocessor systems. For example, in response to a request to update a target memory location at a Level-2 (L2) cache shared among multiple local processing units each having a Level-1 (L1) cache, a lookup based on the target memory location may be performed in a snoop filter that tracks entries in the L1 caches. If the lookup misses the snoop filter and the snoop filter lacks space to store a new entry, a victim entry to evict from the snoop filter may be selected and a request to invalidate every cache line that maps to the victim entry may be sent to at least one of the processing units with one or more cache lines that map to the victim entry. The victim entry may then be replaced in the snoop filter with the new entry corresponding to the target memory location.