A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

A microcontroller unit (MCU) includes a central processing unit (CPU) that reads a program from a flash read-only memory (ROM) and executes a process, a remapping register that stores a read destination of the flash ROM to be read by the CPU, an overwrite flag register that stores a flag that determines whether or not to overwrite the program stored in the flash ROM when the CPU is reset, and a dedicated remapping reset register that resets the CPU and the remapping register but does not reset the overwrite flag register when a value indicating resetting of the CPU and the remapping register is written thereto.

Systems, methods and apparatus of optimizing neural network computations of predictive maintenance of vehicles. For example, a data storage device of a vehicle includes: a host interface configured to receive a sensor data stream from at least one sensor configured on the vehicle; at least one storage media component having a non-volatile memory; and a controller. The non-volatile memory is configured into multiple partitions (e.g., namespaces) having different sets of memory operation settings configured for different types of data related to an artificial neural network (ANN). The partitions include an output partition configured to store output data from the ANN. The sensor data stream is applied in the ANN to predict a maintenance service of the vehicle. The memory units of the input partition can be configured for cyclic sequential overwrite of selected outputs that are updated less frequently than inputs to the ANN.

Method, systems and apparatuses may provide for technology that identifies first data and second data to be stored in a data storage. Each of the first data and the second data are in a first data format. Some technology may also interleave the first data with the second data. The interleaved first and second data are in a second data format. The second data format is different from the first data format.

A method for communicating between motorized power tools includes establishing, using a physical interface of a first power tool, a wireless radio link between the first power tool and a second power tool. The first power tool has a first motor and the second power tool has a second motor. A signal is received over the wireless radio link, via the physical interface, at the first power tool from the second power tool using a first wireless communication protocol. The signal includes an identifier. The second power tool is verified as authorized to send the signal to the first power tool based on the identifier. A tool component of the first power tool is controlled responsive to the signal.

A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

A digital signal processing device includes: a delay means that delays audio data in units of sampling periods; and a control means that writes audio data to a first buffer memory one word at a time in sequence at a sampling period, performs control to burst transfer burst length audio data to a DRAM from the first buffer memory, performs control to burst transfer the burst length audio data to a second buffer memory from the DRAM, and outputs audio data to the delay means from the second buffer memory one word at a time in sequence at the sampling period, in which a delay time of audio data output by the delay means is determined by a combination of a delay time of multiple sampling period units depending on a burst length of the DRAM and a delay time of a sampling period unit of the delay means.

A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.

An approach is provided for skipping, i.e., not processing and/or deleting, near-memory processing commands when one or more skip criteria are satisfied. Examples of skip criteria include, without limitation, specific operations, specific operands, and combinations of specific operations and specific operands. The approach is implemented at one or more memory command processing elements in the memory pipeline of a processor, such as memory controllers, caches, queues, and buffers, etc. Implementations include exceptions to skipping in certain situations and software support for configuring skip criteria, including particular operations and operands for which skip checking is performed. The approach provides the benefits of reducing command bus traffic and power consumption while maintaining functional correctness.

Embodiments of the present disclosure include techniques storing and retrieving data. In one embodiment, sub-matrices of data are stored as row slices and column slices. A fetch circuit determines if particular slices of one sub-matrix, when combined with corresponding slices of another sub-matrix, produce a zero result and need not be retrieved. In another embodiment, the present disclosure includes a memory circuit comprising memory banks and sub-banks. The sub-banks store slices of sub-matrices. A request moves between serially configured memory banks and slices in different sub-banks may be retrieved at the same time.