Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processer further performs the single-frame TLB refresh operation to purge the translation for the single frame.

A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.

A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.

An electronic device includes remapping hardware, a processor, and a Northbridge IC. The remapping hardware converts a virtual address included in an unconverted DMA request into a physical address. The processor executes software to configure the remapping hardware. The Northbridge IC sends the physical address to the processor. When the software changes the configuration of the remapping hardware, the remapping hardware outputs a data draining request to the Northbridge IC. When the Northbridge IC receives the data draining request at a first time, the Northbridge IC suspends unconverted DMA requests after the first time until a second time, and outputs a first data draining response to the remapping hardware at the second time. The remapping hardware receives the first data draining response and notifies the processor that the data draining request has been completed.

A metadata processing method includes a network interface card in a storage device that receives an input/output (I/O) request, where the I/O request includes a data read request or a data write request; the network interface card executes a metadata processing task corresponding to the I/O request; and when determining that the metadata processing task fails to be executed, the network interface card requests a CPU in the storage device to execute the metadata processing task.

A serial transmission controller for processing data transmissions between a memory and an external device is provided. The serial transmission controller includes a microcontroller, a scheduling unit, a transmission unit, and an interception control unit. The microcontroller obtains pipe data from the memory. The microcontroller reads a transfer request block from the memory according to the pipe data. The scheduling unit generates a transmission request according to the pipe data and the transfer request block. The transmission unit transmits a packet of the transfer request block according to the transmission request, and correspondingly generates a transmission response. When the interception control unit receives the transmission response, and the data length that has not been transmitted in the transfer request block is greater than 0, the interception control unit notifies the transmission unit to continue to transmit a next packet of the transfer request block.

In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

In at least some embodiments, a processor core generates one or more store operations by executing one or more store instructions in an instruction sequence. The one or more store operations are marked as a high priority store operations in response to detecting, in the instruction sequence, a window opening instruction and a window closing instruction bounding the one or more store instructions and are not so marked otherwise. The one or more store operations are buffered in a store queue associated with a cache memory of the processor core. Handling of the one or more store operations in the store queue is expedited in response to the one or more store operations being marked as high priority store operations and not expedited otherwise.

In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation in response to the store instruction being marked as high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.