G06F2212/304

LRU LIST REORGANIZATION FOR FAVORED AND UNFAVORED VOLUMES

A method for improving cache hit ratios for selected storage elements within a storage system includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method periodically scans the first LRU list for non-favored storage elements that have changed to favored storage elements, and the second LRU list for favored storage elements that have changed to non-favored storage elements. A corresponding system and computer program product are also disclosed.

Memory system, memory controller and method for operating memory controller
11126552 · 2021-09-21 · ·

Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.

Hybrid Memory Systems with Cache Management
20210271599 · 2021-09-02 · ·

In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory module includes volatile memory, non-volatile memory, and an internal cache. The internal cache is communicably coupled with the volatile memory and the non-volatile memory. Whether to execute a memory access request is determined by operation of the memory module. In response to the inability of the memory access request to be executed, a data transferring process is performed to copy data between the volatile memory and the non-volatile memory via the internal cache.

Cache page retention based on page cost

A method for retaining data pages in a cache is disclosed. In one embodiment, such a method stores multiple data pages in a cache. The method calculates, for each data page, a cost associated with promoting the data page from persistent storage media to the cache. The cost takes into account any data transformations (decryption, decompression, etc.) that are needed to promote the data page from the persistent storage media to the cache. In certain embodiments, the cost is represented as a score that is assigned to each data page. The method retains each data page in the cache for an amount of time that is related to its cost, such that data pages with a higher cost are retained in the cache longer than data pages with a lower cost. A corresponding apparatus and computer program product are also disclosed.

MRAM noise mitigation for write operations with simultaneous background operations

A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

Multi-power-domain bridge with prefetch and write merging

Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.

Storage system
10970237 · 2021-04-06 · ·

A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.

Hybrid Memory Systems with Cache Management
20210056029 · 2021-02-25 · ·

In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory access request is transmitted by operation of a host memory controller to a memory module via a memory interface. Whether to execute the memory access request is determined by operation of the memory module according to one or more specifications of the memory interface. In response to determining the memory access request cannot be executed according to the one or more specifications of the memory interface, the host memory controller is notified by the memory module and halted. Respective actions are performed by operation of the memory module based on the memory access request and a type of the memory module.

CACHE PAGE RETENTION BASED ON PAGE COST

A method for retaining data pages in a cache is disclosed. In one embodiment, such a method stores multiple data pages in a cache. The method calculates, for each data page, a cost associated with promoting the data page from persistent storage media to the cache. The cost takes into account any data transformations (decryption, decompression, etc.) that are needed to promote the data page from the persistent storage media to the cache. In certain embodiments, the cost is represented as a score that is assigned to each data page. The method retains each data page in the cache for an amount of time that is related to its cost, such that data pages with a higher cost are retained in the cache longer than data pages with a lower cost. A corresponding apparatus and computer program product are also disclosed.

MULTICORE SHARED CACHE OPERATION ENGINE

Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.