In various embodiments, a memory interface unit organizes data within a memory tile to facilitate efficient memory accesses. In an embodiment, a memory tile represents a portion of memory that holds multiple chunks of data, where each chunk is stored either in a non-compressed or in a smaller compressed data format. In an embodiment, the tile is organized to pack multiple compressed chunks together so that multiple compressed chunks can be retrieved from memory with a single read access. In another embodiment, the tile is organized to store redundant copies of compressed chunks so that a compressed chunk can be quickly decompressed within a tile without having to relocate other compressed chunks in the tile. Additional embodiments are further disclosed for allowing efficient accesses to both compressed and non-compressed data.

In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory access request is transmitted by operation of a host memory controller to a memory module via a memory interface. Whether to execute the memory access request is determined by operation of the memory module according to one or more specifications of the memory interface. In response to determining the memory access request cannot be executed according to the one or more specifications of the memory interface, the host memory controller is notified by the memory module and halted. Respective actions are performed by operation of the memory module based on the memory access request and a type of the memory module.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A memory system includes a nonvolatile memory that includes a plurality of regions; a volatile memory; and a controller that is connected to the nonvolatile memory and the volatile memory. The controller is configured to store in the volatile memory a plurality of first counter values each indicating the number of times each of the plurality of regions has been accessed and a plurality of second counter values respectively corresponding to the plurality of first counter values, and write the first counter value of a first region of the plurality of regions to the nonvolatile memory in response to the second counter value of the first region being equal to or more than a threshold value.

Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.

Embodiments of the present invention relate to a memory system, a memory device, a memory controller and an operating method thereof. A partial mapping table including some of plural pieces of mapping information between physical addresses and logical addresses, which are included in a mapping table stored in the memory device, is cached, a piece of mapping information corresponding to data indicated by a command is referred to in the partial mapping table, and whether to perform an update for a reference-related parameter of the piece of mapping information is controlled depending on a size of the data, thereby improving cache efficiency for mapping informations for processing a request from a host and through this, increasing the success rate of a cache hit.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A memory system includes: a non-volatile first memory; a second memory which is a set-associative cache memory including a plurality of ways; and a memory controller The first memory stores a plurality of pieces of first information each of which associates a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory. The plurality of pieces of first information includes second information and third information. The second information associates a logical address with a physical address in a first unit. The third information associates a logical address with a physical address in a second unit different from the first unit. The memory controller caches the second information only in a first way. The memory controller caches the third information only in a second way different from the first way.

A first storage controller includes a first processor, a first memory, and a first switch having a first port. A second storage controller includes a second processor, a second memory, and a second switch having a second port. A storage system connects the first port and the second port by a first link. The first processor and the first switch are connected by a second link configured to transfer user data and a third link configured to transfer control data. The second processor and the second switch are connected by a fourth link configured to transfer user data and a fifth link configured to transfer control data. The first port and the second port transfer the control data in preference to the user data on the first link.

A storage device includes a memory device including a metadata area and a journal data area. A memory controller is configured to control the memory device to write a metadata block to the metadata area and to write a journal data block to the journal data area. The metadata block includes metadata, and the journal data block includes both journal data and metadata storage information. The journal data includes log information pertaining to the metadata, and the metadata storage information includes information pertaining to storage of the metadata block.