A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.

A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.

Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

A method, a computing device, and a non-transitory machine-readable medium for changing ownership of a storage volume from a first controller to a second controller without flushing data, is provided. In the system, the first controller is associated with a first DRAM cache comprising a primary partition that stores data associated with the first controller and a mirror partition that stores data associated with the second controller. The second controller in the system is associated with a second DRAM cache comprising a primary partition that stores data associated with the second controller and the mirror partition associated with the first controller. Further, the mirror partition in the second DRAM cache stores a copy of a data in the primary partition of the first DRAM cache and the mirror partition in the first DRAM cache stores a copy of a data in the primary partition of the second DRAM cache.

An information processing system comprising a storage device and an information processing device, wherein the information processing device includes a data holding unit which holds first data, a first detection unit which detects a first state of access, and a transmission unit which transmits the first state of access detected by the first detection unit to the storage device, and the storage device includes a storage unit which stores second data, a reception unit which receives the first state of access transmitted from the transmission unit, a second detection unit which detects a second state of access, which is a state of access to the second data, and a control unit which rearranges the second data in the storage unit on the basis of the states of access.

Technologies for dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support. The computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values. The computing device generates an initial secure enclave memory image that includes the root value of the hash tree. At runtime, the computing device accesses a chunk of the executable image from within the secure enclave, which generates a page fault. In response to the page fault, the secure enclave verifies the associated chunk based on the hash tree and accepts the chunk into the secure enclave in response to successful verification. The root value of the hash tree is integrity-protected. Other embodiments are described and claimed.

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

A hybrid drive and associated methods increase the rate at which data are transferred to a nonvolatile storage medium in the hybrid drive. By using a large nonvolatile solid state memory device as cache memory for a magnetic disk drive, a very large number of write commands can be cached and subsequently reordered and executed in an efficient manner. In addition, strategic selection and reordering of only a portion of the write commands stored in the nonvolatile solid state memory device increases efficiency of the reordering process.

Embodiments are directed to providing a secure address translation service. An embodiment of a system includes memory for storage of data, an IOMMU coupled to the memory, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the memory, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the memory pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.