To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.

Determining and using the ideal size of memory to be transferred from high speed memory to a low speed memory may result in speedier saves to the low speed memory and a longer life for the low speed memory.

Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.

Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.

Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (1/0) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.