A storage device and a method of operating the storage device include various memory devices. The storage device includes a plurality of memory devices each including at least one or more read cache memory blocks and a plurality of main memory blocks; and a memory controller configured to spread and store data stored in an identical memory device, having a read count representing a number of read requests and exceeding a threshold value, among data stored in the plurality of main memory blocks, to the at least one or more read cache memory blocks included in each of the plurality of memory devices.

A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

Aspects disclosed herein include memory controllers employing memory capacity compression, and related processor-based systems and methods. In certain aspects, compressed memory controllers are employed that can provide memory capacity compression. In some aspects, a line-based memory capacity compression scheme can be employed where additional translation of a physical address (PA) to a physical buffer address is performed to allow compressed data in a system memory at the physical buffer address for efficient compressed data storage. A translation lookaside buffer (TLB) may also be employed to store TLB entries comprising PA tags corresponding to a physical buffer address in the system memory to more efficiently perform the translation of the PA to the physical buffer address in the system memory. In certain aspects, a line-based memory capacity compression scheme, a page-based memory capacity compression scheme, or a hybrid line-page-based memory capacity compression scheme can be employed.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

A memory system may include a storage device and a controller. The storage device may include a non-volatile memory device. The controller may include a device memory. The controller may control operations of the non-volatile memory device in accordance with a request of a host device. wherein the controller includes a map data management circuit configured to cache one or more segments from a plurality of map segment groups stored in the storage device, each segment having information including a reference count and mapping relationships between logical addresses and physical addresses, detect, among the one or more cached segments, an upload target segment in which the reference count is greater than a predetermined count and transmit, when a predetermined number or greater of upload target segments are detected within a first map segment group, the predetermined number or greater of upload target segments to the host device.

A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.

To improve performance of a storage system. The storage system includes a plurality of storage nodes that communicate via a network. Each of the plurality of storage nodes includes one or more controllers. At least one controller in the controllers specifies at least two controllers that allocate a cache sub-area where write data is stored based on a controller that receives the write data from a host and a controller that processes the write date, and the cache sub-area is allocated in the specified controllers.

An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.