G06F2212/306

Pre-fetching address translation for computation offloading

Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

Coherency control
12423236 · 2025-09-23 · ·

An apparatus comprises an non-inclusive cache (14) configured to cache data and coherency control circuitry (16). The coherency control circuitry is configured to look up the non-inclusive cache in response to a coherent access request from a first requestor (4). In response to determining that the coherent access request can be serviced using data stored in a matching entry of the non-inclusive cache, the coherency control circuitry references snoop-filter information associated with the matching entry to determine whether the first requestor can use the data stored in the matching entry without waiting for a response to a snoop of a coherent cache (8).