Embodiments for optimizing dynamic resource allocations in a disaggregated computing environment. A new workload is assigned to a subset of a plurality of processors, the subset of processors assigned a subset of a plurality of cache devices. A determination is made that the new workload is categorized as a cache-friendly workload having a memory need which can be met primarily by the subset of cache devices by identifying that underlying data necessitated by the new workload resides primarily within the subset of cache devices. Pursuant to determining the new workload is the cache-friendly workload, a cache related action is performed to increase performance of the new workload executed by the subset of processors and commensurately executes additional workloads performed by other ones of the plurality of processors within the disaggregated computing environment.

In some examples, during execution of an application as an application asset is called, an asset map that is stored in a persistent memory device is searched for an asset identifier associated with the application asset. Using this asset identifier, an application asset stored in the persistent memory device is located. The persistent memory device is directly accessed by a processor executing the application. The processor processes the application asset from its location in the persistent memory device.

A virtual disk is provided to a computing environment. The virtual disk includes identity information to enable identification of a virtual machine within the computing environment. A size of the virtual disk is increased within the computing environment to enable the virtual disk to act as a storage for the identity information and as a cache of other system data to operate the virtual machine. The virtual machine is booted within the computing environment. The virtual machine is configured to at least access the virtual disk that includes both identity information and caches other system data to operate the virtual machine. Related apparatus, systems, techniques and articles are also described.

Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

A memory system includes: a normal memory area suitable for storing normal data; a security memory area suitable for storing security data; a first row hammer detection circuit suitable for sampling and counting a portion of rows that are activated in the normal memory area to select first rows that need to be refreshed; and a second row hammer detection circuit suitable for counting all rows that are activated in the security memory area to select second rows that need to be refreshed.

A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

Technology for enabling a hypervisor to perform copy on write features on encrypted storage of a virtual machine. An example method may involve: receiving, by a guest program from a hypervisor, an indication that identifies a first storage block of a first virtual machine, wherein the first storage block is write protected by the hypervisor; identifying, by the guest program, a second storage block of a second virtual machine; and copying, by the guest program, data of the first storage block to the second storage block, wherein the data of the first storage block and data of the second storage block are encrypted using different cryptographic inputs.

A method for an in-memory distributed cache includes receiving a write request from a client device to write a block of client data in random access memory (RAM) of a memory host and determining whether to allow the write request by determining whether the client device has permission to write the block of client data at the memory host, determining whether the block of client data is currently saved at the memory host, and determining whether a free block of RAM is available. When the client device has permission to write the block of client data at the memory host, the block of client data is not currently saved at the memory host, and a free block of RAM is available, the write request is allowed and the client is allowed to write the block of client data to the free block of RAM.

Disclosed is an approach for implementing a metadata cache in a virtualization system. A self-adaptive approach is provided to keep compressed and uncompressed entries together in cache. Along with adaptive nature, disclosed is an approach to prioritize critical workloads for the cache.

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.