A data storage device and method for host-initiated cached read to recover corrupted data within timeout constraints are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive a read look-ahead command from a host to perform a read look-ahead of a first logical address; receive a read command from the host to read a second logical address; and execute the read look-ahead command by performing the following as background operations while executing the read command: read data for a location in the non-volatile memory that corresponds to the first logical address; correct an error in the data; and cache the corrected data in the volatile memory. The cached corrected data can be sent back to the host in response to the host requesting a read of the same logical address. Other embodiments are provided.

Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

A storage device having improved operation speed may include a main memory configured to store first to N-th meta data, a cache memory including first to N-th dedicated areas respectively corresponding to areas in which the first to N-th meta data are stored, and a processor configured to store data accessed according to requests provided from a host among the first to N-th meta data in the first to N-th dedicated areas, respectively. A size of the first to N-th dedicated areas may be determined according to the number of times each of the first to N-th meta data is accessed by the requests.

Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

In various embodiments, an electronic device may include a display, a memory including a first space storing no data and a second space storing data, and a processor. The processor may be configured to control the electronic device to: receive an input for inputting a setting value for a fast data storage mode of the memory, to allocate a predetermined size of a free space of a file system of the electronic device as a temporary memory space for the fast data storage mode based on the setting value for the fast data storage mode, to control the memory to allocate a predetermined size of the first space as a borrowed space for the fast data storage mode corresponding to the size of the temporary memory space, to recognize occurrence of an event for starting data storage through the fast data storage mode, and to control the memory to perform the data storage using the borrowed space through the fast data storage mode in response to the occurrence of the event.

In a storage medium management method, a controller receives an address space request that requests the provision of an address space in a target storage medium for an operating system, the target storage medium having two different types of storage media. The Controller determines a first address space in the target storage medium based on the address space request, and a physical address of the first address space to a target virtual address, which is managed by the operating system. The controller then provides to an operating system a first address space requested by the address space request, such that the first address space is directly managed by an operating system, without manual configuration or restart of an electronic device.

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Disclosed are a solid state drive and a write operation method. The solid state drive comprises: a controller, receiving write data from outside and comprising a first cache unit for storing the write data; a Flash memory, receiving the write data sent by the first cache unit according to a first instruction of the controller; a second cache unit, storing the write data from the first cache unit as backup data, and sending the backup data to the Flash memory according to a second instruction of the controller. The second instruction is obtained after the write data fails to be written into the Flash memory under the first instruction, so that the backup data can continue to be called if write operation fails. By combining advantages of the first and second cache units, efficiency and quality of write operations are improved and bandwidth requirements are lowered.

Methods, systems, and devices for configurable flush operation speed are described. Before executing a flush operation at a first portion of a cache including single-level cells (SLCs), a memory system may communicate parameters associated with data stored in the first portion of the cache to a host system. The host system may then identify another portion of the cache (e.g., including either SLCs or multi-level cells (MLCs)) for the flush operation based on the parameters and a speed of a flush operation associated with the other portions of the cache. The host system may indicate the identified portion of the cache to the memory system and the memory system may execute a flush operation at the first portion of the cache. For example, the memory system may write a subset of the data stored at the first portion of the cache to a second portion of the cache.