Patent classifications
G06F2212/313
Adaptive power loss management for data storage devices
A Data Storage Device (DSD) includes at least one Non-Volatile Memory (NVM) configured to store data and a Non-Volatile Cache (NVC). Write data is stored in a volatile memory in preparation for writing the write data in the at least one NVM. In response to a power loss of the DSD, at least a portion of the data stored in the volatile memory is transferred from the volatile memory to the NVC and one or more parameters are determined for deriving a margin representing an additional amount of data for transfer from the volatile memory to the NVC using a remaining power following a power loss. A size of the NVC is adjusted based at least in part on the derived margin.
MANAGING MEMORY MAINTENANCE OPERATIONS IN A MEMORY SYSTEM HAVING BACKING STORAGE MEDIA
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.
PROVIDING ROLLING UPDATES OF DISTRIBUTED SYSTEMS WITH A SHARED CACHE
Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a data item key corresponding to a request from a user profile operating on a media player and receiving a version identifier corresponding to a first version of an application operating on the media player. It is determined that a shared cache includes a first value and second value for the data item key. A key component is generated corresponding to the user profile. Both the generated key component and the data item key are provided to the shared cache, and the first value of the data item as stored in the shared cache is received. The first value of the first version of the data item is updated.
PRIORITY-BASED STORAGE AND ACCESS OF COMPRESSED MEMORY LINES IN MEMORY IN A PROCESSOR-BASED SYSTEM
In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time
Multi-Level System Memory With Near Memory Scrubbing Based On Predicted Far Memory Idle Time
An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.
Data compression in a multi-layer distributed datastore
A method for compressing is provided. The method including receiving a block of data to store on at least one physical disk; determining whether to store the data in a data log as uncompressed or compressed data based on a determined size of resulting compressed data. When the method determines to store the data as compressed, compressing the data and storing the compressed data in at least one sector in the data log. Otherwise, the method stores the data, uncompressed, in a plurality of sectors in the data log. The method generates a one or more state bits indicating (i) whether the data is stored as uncompressed or compressed, and (ii) if the data is stored as compressed, a size of the compressed data. The method then stores the one or more state bits in an entry of a logical map table associated with an LBA that corresponds to the data block.
Command Tunneling in a Hybrid Data Storage Device
Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A top level controller circuit directs a selected access command one of the HDD controller circuit or the SSD controller circuit responsive to a selected parameter associated with the selected access command. In a normal mode, the top level controller circuit directs a transfer of data between the host and the HDD controller circuit and handles host interface communications. In a tunneling mode, the top level controller circuit directly connects the HDD controller circuit to the host device. In this way, tunnel mode bypasses processing operations required by the top level controller circuit. Tunnel mode and normal mode may be selected on a command-by-command basis.
Storage of tree data structures
Disclosed herein is a computer-implemented method for storing Merkle tree data in memory. The Merkle tree data comprising uncle node data, first nephew node data and second nephew node data. The computer implemented method comprises determining a first nephew node memory address, determining a second nephew node memory address, storing the uncle node data at the uncle node memory address, storing the first nephew node data at the first nephew node memory address, and storing the second nephew node data at the second nephew node memory address. The first nephew node memory address is less than the uncle node memory address and the second nephew node memory address is greater than the uncle node memory address, or the first nephew node memory address is greater than the uncle node memory address and the second nephew node memory address is less than the uncle node memory address.
Efficient key collision handling
Inventive aspects include a key value store engine including non-volatile memory configured to store key-value inode descriptors each including a key and an associated value. The key value store engine can include a volatile memory to store a key hash tree and a collision hash tree. The key hash tree can include nodes each having a hash of one of the keys. The collision hash tree can include nodes each having a collided hash associated with two or more different keys. Each of the nodes of the key hash tree can include a collision flag indicating whether two or more different hashes correspond to a collided hash. The volatile memory can store a collision linked list including linked list nodes each having a key-value inode number indicating a location of a corresponding key-value inode descriptor stored in the non-volatile memory. The key value store engine can include a key value logic section.
Systems and methods for persistent cache logging
A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log may be divided into segments, each comprising a set of log entries. Data admitted into the cache may be associated with respective log segments. Cache data may be associated with the log segment that corresponds to the cache storage operation in which the cache data was written into the cache. The backing store of the data may be synchronized to a particular log segment by identifying the cache data pertaining to the segment (using the associations), and writing the identified data to the backing store. Data lost from the cache may be recovered from the log by, inter alia, committing entries in the log after the last synchronization time of the backing store.