Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Disclosed are a method and apparatus for storing and querying time series data. The method includes: determining a data type of data to be stored; compressing the data to be stored by a data compression method corresponding to the data type; storing compressed data to a data storage table corresponding to the data type; receiving a query request including a query data type and a query time condition; querying target data that meets the query time conditions from a data storage table corresponding to the query data type. In the embodiments of the present disclosure, different compression methods are adopted for different types of data, which improves the compression efficiency of time series data and save storage resources. Moreover, when performing data query, time series data that meets a query time condition is searched in a data storage table corresponding to a query data type, which improves the query efficiency of different types of time series data.

A method for compressing data in a local cache of a web server is described. A local cache compression engine accesses values in the local cache and determines a cardinality of the values of the local cache. The local cache compression engine determines a compression rate of a compression algorithm based on the cardinality of the values of the local cache. The compression algorithm is applied to the cache based on the compression rate to generate a compressed local cache.

Low latency in a non-uniform cache access (“NUCA”) cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.

A method, system, and computer program product for local DRAM caching of storage class memory elements are provided. The method identifies a cache line with a cache address in a local dynamic random-access memory (DRAM). The cache line is compressed within the local DRAM to generate a compressed cache line and an open memory space within the local DRAM. A cache tag is generated in the open memory space and a validation value is generated in the open memory space for the compressed cache line. The method determines a cache-hit for the cache line based on the cache address, the cache tag, and the validation value.

Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.

Data may be transferred from a volatile memory to a non-volatile memory using a persistent power enabled on-chip data processor upon detecting a power loss from a primary power source. The one or more emergency power supplies are attached to the volatile memory, the non-volatile memory, and the persistent power enabled on-chip data processor to assist with the transferring of data.

Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

A memory swapping method and apparatus are provided. The method includes: selecting n to-be-swapped-out pages; compressing the n to-be-swapped-out pages into n compressed blocks, and buffering the n compressed blocks in a compressed data buffer area; organizing at least one of the n compressed blocks into m to-be-written units; and writing the m to-be-written units into a swap area of a non-volatile storage device in a maximum of m batches, where at least one to-be-written unit is stored in a segment of continuous space in the swap area. The method reduces a quantity of write times during memory swapping, thereby prolonging a service life of the non-volatile storage device.

A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.