A storage apparatus includes: a flash memory that provides a storage area; a controller that controls writing and reading of data to and from the storage area; and a buffer memory that temporarily stores data to be written in the storage area, in which the controller selects one compression method from a first reversible compression method and a second reversible compression method based on access performance to the flash memory, and determines to compress data based on the selected one compression method and to write the compressed data to the storage area, and the first reversible compression method has a lower compression ratio and a slower compression speed than the second reversible compression method.

The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.

For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

In write processing of a data set group to be written to be one or more data sets to be written, a storage system performs encoding processing including processing for generating a data model showing regularity of the data set group to be written and having one or more input values as an input and the data set group as an output. In the write processing, the storage system writes the data model generated in the encoding processing and associated with a key of the data set group to be written.

A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.

A system and method for memory compression for deep learning networks. The method includes: compacting an input data stream by identifying a bit width necessary to accommodate the value from the input data stream with the highest magnitude; storing a least significant bits of the input data stream in a first memory store, the number of bits equal to the bit width, wherein if the value requires more bits than those currently left unused in the first memory store, the remaining bits are written into a second memory store; and outputting the value of the first memory store, as a consecutive part of a compressed data stream, with an associated width of the data in the first memory store when the first memory store becomes full and copying the value of the second memory store to the first memory store; and decompressing the compressed data stream.

Techniques for cache management involve: determining respective elimination scores of a plurality of entries in a cache based at least in part on compression rates of data blocks corresponding to the plurality of entries, the elimination score being proportional to the compression rate; and removing, from the cache, at least one entry with a relatively low elimination score among the plurality of entries. Such techniques are able to optimize the retention and elimination strategies for entries in a cache, thus increasing payoffs for using the cache.

A memory management system includes a physical memory associated with a computing device and a memory manager. The memory manager is configured to manage a shared memory cache as part of a compression of the physical memory using a cache compression algorithm, wherein a compression block size for the compression is a single cache line size. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses a memory descriptor defined by an STT entry having a cache line map and a plurality of sector pointers to load cache from the physical memory to a level 3 Cache. The cache line map contains cache line metadata including a size of each cache line, a location of the cache line in one of the sectors pointed to by the STT entry, and a plurality of flags.

Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.