A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

The application provides an information processing device, system and method. The information processing device mainly includes a storage module and a data processing module, where the storage module is configured to receive and store input data, instruction and output data, and the input data includes one or more key features; the data processing module is configured to identify the key features included in the input data and score the input data in the storage module according to a judgment result. The information processing device, system and method provided by the application automatically scores text, pictures, audio, video, and the like instead of manually scoring, which is more accurate and faster.

Implementations of the disclosure provide systems and methods for receiving, by a processing device, a request for an application image. A sequence of commands associated with the application image and a value of a parameter associated with the sequence of commands is received. Responsive to determining that the sequence of commands has been previously executed with the value of the parameter, the processing device retrieves, from a cache, a result of executing the sequence with the value of the parameter. The application image is built using the first result of executing the sequence.

Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between the first thread and the second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is sharable based on the alias table entry.

A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.

Managing a cache includes parsing a physical address of a data block to determine a partition identifier (ID) and a tag; the partition ID compared against a partition table storing partition IDs. The partition table indicates at least one way partition and at least one set partition corresponding to the partition ID. Based on the partition table, a way partition is determined at which to store the data block, corresponding to a subset of columns of a cache and, based on the partition table and the tag, a set partition is determined at which to store the data block, corresponding to a subset of rows of the cache. A cache address is generated for the data block within a first region of the cache corresponding to an intersection of the way partition and the set partition. The data block is stored to the cache according to the cache address.

A method of verifying authenticity of a speculative load instruction is disclosed which includes receiving a new speculative source-destination pair (PAIR), wherein the source represents a speculative load instruction and the destination represents an associated destination virtual memory location holding data to be loaded onto a register with execution of the source, checking the PAIR against one or more memory tables associated with non-speculative source-destination pairs, if the PAIR exists in the one or more memory tables, then executing the instruction associated with the source of the PAIR, if the PAIR does not exist, then i) waiting until the speculation of the source instruction has cleared as being non-speculative, ii) updating the one or more memory tables, and iii) executing the instruction associated with the source, and if the speculation of the source instruction of the PAIR does not clear as non-speculative, then the source is nullified.