G06F2212/453

Accelerating software builds

A set of source files is stored in a shared storage repository for nodes of a distributed computing environment for software compilation. An object file is created based on at least a portion of the set of source files. A directed acyclic graph (DAG) is generated corresponding to a group of software build tasks and the relationship between the software build tasks based on the set of source files. A replication factor for the object file is determined based on the number of relationships of the object file identified from the DAG. The object file is stored in a local memory cache of at least one of the number of the nodes, wherein the number of the nodes is based on the replication factor for the object file.

Message cache management for message queues

A method and apparatus for message cache management for message queues is provided. A plurality of messages from a plurality of enqueuers are enqueued in a queue comprising one or more shards, each shard comprising one or more subshards. A message cache is maintained in memory. Enqueuing a message includes enqueuing the message in a current subshard of a particular shard, which includes storing the message in a cached subshard corresponding to the current subshard of the particular shard. For each dequeuer-shard pair, a dequeue rate is determined. Estimated access time data is generated that includes an earliest estimated access time for each of a plurality of subshards based on the dequeuer-shard pair dequeue rates. A set of subshards is determined for storing as cached subshards in the message cache based on the earliest estimated access times for the plurality of subshards.

REUSE OF A RELATED THREAD'S CACHE WHILE RECORDING A TRACE FILE OF CODE EXECUTION
20180113789 · 2018-04-26 ·

Reusing a related thread's cache during tracing. An embodiment includes executing a first thread at a processing unit while recording a trace to a first buffer. During execution, a context switch from the first thread to a second thread at the same processing unit is detected. Based on the context switch, it is determined that the second thread is related to the first thread, and that it is being traced to a separate second buffer. Based on this determination, a cache of the first thread is reused. The reuse includes recording a first identifier in the first buffer, and recording a second identifier in the second buffer. The first and second identifiers provide a linkage between the first buffer and the second buffer. Execution of the second thread is then initiated, while recording a trace to the second buffer, and without invalidating logging state of a cache.

FACILITATING RECORDING A TRACE FILE OF CODE EXECUTION USING INDEX BITS IN A PROCESSOR CACHE
20180113788 · 2018-04-26 ·

Facilitating recording a trace file of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, index bits for the cache line are set. Setting the index bits includes one of: (i) setting the bits to a reserved value when the operation is a write operation and tracing is disabled, (i) setting the bits to an index of the processing unit when the operation is a write operation and the bits are already set to a value other than the index of the processing unit, or (iii) setting the bits to the index of the processing unit when the operation is a read operation that is consumed by the processing unit and the bits are already set to a value other than the index of the processing unit.

ACCELERATING SOFTWARE BUILDS
20180081652 · 2018-03-22 ·

A set of source files is stored in a shared storage repository for nodes of a distributed computing environment for software compilation. An object file is created based on at least a portion of the set of source files. A directed acyclic graph (DAG) is generated corresponding to a group of software build tasks and the relationship between the software build tasks based on the set of source files. A replication factor for the object file is determined based on the number of relationships of the object file identified from the DAG. The object file is stored in a local memory cache of at least one of the number of the nodes, wherein the number of the nodes is based on the replication factor for the object file.

ACCELERATING SOFTWARE BUILDS
20180081653 · 2018-03-22 ·

A set of source files is stored in a shared storage repository for nodes of a distributed computing environment for software compilation. An object file is created based on at least a portion of the set of source files. A directed acyclic graph (DAG) is generated corresponding to a group of software build tasks and the relationship between the software build tasks based on the set of source files. A replication factor for the object file is determined based on the number of relationships of the object file identified from the DAG. The object file is stored in a local memory cache of at least one of the number of the nodes, wherein the number of the nodes is based on the replication factor for the object file.

MESSAGE CACHE MANAGEMENT FOR MESSAGE QUEUES

A method and apparatus for message cache management for message queues is provided. A plurality of messages from a plurality of enqueuers are enqueued in a queue comprising one or more shards, each shard comprising one or more subshards. A message cache is maintained in memory. Enqueuing a message includes enqueuing the message in a current subshard of a particular shard, which includes storing the message in a cached subshard corresponding to the current subshard of the particular shard. For each dequeuer-shard pair, a dequeue rate is determined. Estimated access time data is generated that includes an earliest estimated access time for each of a plurality of subshards based on the dequeuer-shard pair dequeue rates. A set of subshards is determined for storing as cached subshards in the message cache based on the earliest estimated access times for the plurality of subshards.

Reconfigurable cache hierarchy framework for the storage of FPGA bitstreams

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

Extended fuse reprogrammability mechanism

An apparatus includes a semiconductor fuse array, disposed on a semiconductor die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored.

Core-specific fuse mechanism for a multi-core die

An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.