Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

An access request processing apparatus comprises, a processor determines an object cache page according to a write request when receiving the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.

A software assist module of a system memory coupled to a host processor provides the ability to offload software operations from the host processor. The software assist module includes a first memory accessed by the host processor via a first chip select signal. The software assist module also includes a software assist controller accessed by the host processor via a second chip select signal. The software assist controller is configured to intercept data related to a software function offloaded from the host processor, where the data is intercepted from a first chip select signal used to access the first memory. The software assist controller utilizes the intercepted data to perform the offloaded function. Based on configuration instructions provided by the host processor via the second chip select signal, the software assist module performs the offloaded function incrementally as function data is intercepted or as a single operation after all data for a function has been intercepted.

In response to receiving a request to perform a transaction with two or more memory operations on one or more tiered data structures, the memory controller: writes a start transaction record to the log stream including a transaction identifier corresponding to the transaction; and performs the two or more memory operations. For a first memory operation associated with a key, the memory controller: writes a new data object in a datastore; assigns, in a key-map, a location of the new data object to the key; maintains an old data object in the datastore whose location was previously assigned to the key; and writes an operation commit record to a log stream upon completion of the first memory operation. In accordance with a determination that the two or more memory operations are complete, the memory controller writes a transaction commit record to the log stream including the transaction identifier.

The instant disclosure provides an accelerated computer system and an accelerated method for writing data into discrete pages. The accelerated method includes executing write commands, with each write command including write data and a write address such that the write address corresponds to a write page of the first pages in a sector of a hard drive, identifying whether the write pages are successive according to the write addresses, acquiring stored data by reading the sector according to the write addresses if the write pages are discrete, writing the data stored in the first pages into the second pages of a memory, writing write data bit by bit into the second pages according to the write addresses, and writing the data stored in the second pages into the first pages.

When a shingled magnetic recording (SMR) hard disk drive (HDD) receives a write command that references one or more target logical block addresses (LBAs) and determines that one or more target LBAs are included in a range of LBAs for which data are stored in a memory of the drive, additional data are written to the media cache of the SMR HDD along with the write data during the same disk access. The additional data include data that are stored in the volatile memory and are associated with one or more LBAs that are adjacent in LBA space to the target LBAs. The one or more LBAs that are adjacent in LBA space to the target LBAs may include a first group of LBAs that is adjacent to and follows the target LBAs and a second group of LBA that is adjacent to and precedes the target LBAs.

Techniques perform storage management. Such techniques involve, in response to an operation to be performed on data in a cache page, determining a first cache page reference corresponding to the cache page, the first cache page reference comprising a pointer value indicating the cache page. Such techniques further involve creating, based on the first cache page reference and the operation, a second cache page reference corresponding to the cache page, the second cache page reference comprising the pointer value. Such techniques further involve performing the operation on the data in the cache page via the second cache page reference. One cache page can correspond to a plurality of cache page references. Additionally, copy of data from one cache page to a further cache page can be effectively avoided, so as to enhance input/output performance and utilization rate of storage space.

Systems, methods, and apparatus including computer-readable mediums for managing memories by overlapping ranges of pages in nonvolatile memory systems are provided. An example memory system includes a memory controller coupled to a memory and configured to: determine a range of logical addresses associated with a command, search particular mapping tables including the range of logical addresses in mapping pages in the memory, determine whether a starting address of the range of logical addresses is in an overlapped range of first and second sequential mapping pages, the overlapped range including logical addresses of one or more mapping tables duplicated in the first and second mapping pages, determine which of the first and second mapping pages from which the particular mapping tables to be loaded based on a result of determining whether the starting address is in the overlapped range, and load the particular mapping tables from the determined mapping page.