Techniques for managing metadata at a control device involve: determining, from a cache page corresponding to user data, a first region for storing raw metadata of the user data, the raw metadata including address information for storing the user data in a storage system; in response to the user data being modified, determining updated metadata of the modified user data to update the raw metadata in the first region; and copying the updated metadata to a high-speed memory shared by the control device and another control device. Accordingly, the techniques are capable of reducing the usage frequency of the high-speed memory, thereby extending the service life of the high-speed memory and reducing cost.

The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.

A method, computer program product, and computer system for executing one of a reboot and a startup process. A write I/O may be received at a DRAM cache. Data may be written to at least two different NVMe devices. When the data of the write I/O is completely written to the at least two different NVMe devices, a response may be sent to a driver layer.

An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.

Techniques to manage usage of a flash-based storage are disclosed. In various embodiments, the execution time of the flash-based storage is divided into quanta. Within each quantum comprising at least a subset of quanta, flash erasures are allowed without restriction up to a prescribed erasure quota. Erasures are throttled within a slack range bound at a lower end by the erasure quota and at an upper end by an upper bound, including by dividing the slack range into two or more intervals and within each interval applying a corresponding erasure control policy, wherein the respective corresponding erasure control policies applied to successive intervals in the slack range become increasingly strict in a stepwise manner.

The present disclosure provided a method, apparatus, and system for caching data. In an embodiment of the present disclosure, the method for caching data comprises: recording, within a recording period for recording access count information of the data, access count information on respective data, wherein the recording period includes a plurality of recording timeslots, wherein the recording of the access count information within a single recording timeslot is restricted, while the access count information within the plurality of recording timeslots is aggregated; and promoting, in response to expiration of the recording period, the respective data into a cache area based on the access count information.

An aspect of performance improvement for an active-active distributed non-ALUA (asymmetrical logical unit assignment) system with address ownerships includes receiving, by a routing module of a content-addressable storage system, an input/output (IO) request; and determining, by the routing module from a table that provides a listing of addresses and compute nodes having ownership to the address, a target location of the IO request. The target location specifies an address. An aspect also includes determining, by the routing module, a mapping between each of the compute modules and a physical path to corresponding storage controllers, an address owner of a storage controller port of a storage controller that owns the address of the IO; selecting a physical path associated with the address owner; and transmitting, by the routing module, the IO request to the storage controller port via a direct call.

Embodiments of the present disclosure provide a computer-implemented method and an apparatus for a storage system. The method comprises: in response to receiving a read request of a first container for data in a storage device, obtaining an identifier associated with the read request; searching for metadata of the read request in a metadata set based on the identifier, the metadata recording addressing information of the read request, the metadata set including metadata of access requests for the storage device during a past period; and in response to finding the metadata of the read request in the metadata set, determining, based on the metadata, a cached page of a second container storing the data; and providing the cached page from the second container to the first container to avoid reading the data from the storage device.

Embodiments of the present disclosure relate to a method and device for cache management. The method includes: receiving an I/O request associated with a processor kernel; in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists; in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance; and adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists.

Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.