A method comprising: receiving, at a vector processor, a request to store data; performing, by the vector processor, one or more transforms on the data; and directly instructing, by the vector processor, one or more storage device to store the data; wherein performing one or more transforms on the data comprises: erasure encoding the data to generate n data fragments configured such that any k of the data fragments are usable to regenerate the data, where k is less than n; and wherein directly instructing one or more storage device to store the data comprises: directly instructing the one or more storage devices to store the plurality of data fragments.

A method comprising: receiving a request to write data at a virtual location; writing the data to a physical location on a persistent storage device; and recording a mapping from the virtual location to the physical location; wherein the physical location corresponds to a next free block in a sequence of blocks on the persistent storage device.

A method comprising: receiving, at a block device interface, an instruction to write data, the instruction comprising a memory location of the data; copying the data to pinned memory; performing, by a vector processor, one or more invertible transforms on the data; and writing the data from the pinned memory to one or more storage devices asynchronously; wherein the pinned memory of the data corresponds to a location in pinned memory, the pinned memory being accessible by the vector processor and one or more other processors.

In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.

When a shingled magnetic recording (SMR) hard disk drive (HDD) performs additional SMR band copy and/or flush operations to ensure that data associated with logical bands that are adjacent or proximate in logical space are stored in physical locations in the SMR HDD that are proximate in physical space. As a result, efficient execution is ensured of read commands that span multiple logical bands of the SMR HDD.

According to one embodiment, a memory system executes, when first address translation data including a first physical address indicating a physical storage location of the nonvolatile memory where data corresponding to a first logical address specified by a host is stored does not exist in a first cache and first compressed address translation data corresponding to the first address translation data exists in a second cache, an operation for storing uncompressed address translation data obtained by decompressing the first compressed address translation data in the second cache in the first cache and an operation for acquiring the first physical address from the uncompressed address translation data.

A method to cache memory requests while accounting for phase change memory cell drift is described. The method includes adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells; adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request; writing the user data of the write memory request to the set of phase change memory cells; and adding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data.

An aspect of cache recovery includes transmitting entries of a write cache (WC) journal (entries) to all nodes and, for each node, recovering the entries, detecting entries with a logical address owned by the node, and performing a recovery operation. The operation includes for each entry, and upon determining the node owns the A2N slice: if the A2N slice has been continuously owned (CO) by the node, and the entry is not owned by the node, marking the entry as WC remote and entry updates are requested from a remote WC owner; if the A2N slice has not been CO by the node, and the entry is not owned by the node, maintaining the entry and continuing write flow operations, marking the entry as WC remote and all entry updates are requested from the remote WC owner and inserting the entry to a recovery list.

An aspect of performance improvement for an active-active distributed non-ALUA (asymmetrical logical unit assignment) system with address ownerships includes receiving, by a routing module of a content-addressable storage system, an input/output (IO) request; and determining, by the routing module from a table that provides a listing of addresses and compute nodes having ownership to the address, a target location of the IO request. The target location specifies an address. An aspect also includes determining, by the routing module, a mapping between each of the compute modules and a physical path to corresponding storage controllers, an address owner of a storage controller port of a storage controller that owns the address of the IO; selecting a physical path associated with the address owner; and transmitting, by the routing module, the IO request to the storage controller port via a direct call.

Techniques for managing metadata at a control device involve: determining, from a cache page corresponding to user data, a first region for storing raw metadata of the user data, the raw metadata including address information for storing the user data in a storage system; in response to the user data being modified, determining updated metadata of the modified user data to update the raw metadata in the first region; and copying the updated metadata to a high-speed memory shared by the control device and another control device. Accordingly, the techniques are capable of reducing the usage frequency of the high-speed memory, thereby extending the service life of the high-speed memory and reducing cost.