Computer-implemented methods using machine learning are provided for generating an estimated cache performance of a cache configuration. A neural network is trained using, as inputs, a set of memory access parameters generated from a non-cycle-accurate simulation of a data processing system comprising the cache configuration and a cache configuration value, and using, as outputs, cache performance values generated by a cycle-accurate simulation of the data processing system comprising the cache configuration. The trained neural network is then provided with sets of memory access parameters generated from a non-cycle-accurate simulation of a proposed data processing system and a selected cache configuration and generates estimated cache performance values for that selected cache configuration.

A computing apparatus is provided. The computing apparatus is configured to receive control information from a host device to control a cache area, generate a cache configuration based on the received control information, determine a first cache area and a second cache area in a memory in the computing apparatus based on the generated cache configuration, cache one or more instructions to the first cache area and cache data to the second cache area, and process a thread based on the one or more cached instructions and the cached data.

A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a number of a plurality of input channels of a plurality of input feature maps, an input feature map tile size, a number of a plurality of output channels of a plurality of output feature maps and an output feature map tile size for a convolutional layer operation. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation. The convolution calculating step is for performing the convolutional layer operation with the input feature maps to produce the output feature maps according to a memory-adaptive processing technique, and the memory-adaptive processing technique includes a dividing step and an output-group-first processing step.

A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

A method, computer program product, and computing system for receiving, at a cache memory system, a write request for writing data to a storage system. A data reduction rate may be predicted for the write request. One or more portions of memory within the storage system may be allocated based upon, at least in part, the predicted data reduction rate for the write request. The write request may be flushed from the cache memory system to the allocated one or more portions of memory within the storage system.

In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time

A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.

Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.