G06F2212/608

SYSTEM AND METHOD OF CONTROLLING CACHE MEMORY RESIDENCY

Apparatuses, systems, and techniques to control operation of a memory cache. In at least one embodiment, cache guidance is specified within application source code by associating guidance with declaration of a memory block, and then applying specified guidance to source code statements that access said memory block.

Flexible dictionary sharing for compressed caches

Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Methods and systems for maintaining cache coherency between nodes in a clustered environment by performing a bitmap lookup in response to a read request from one of the nodes

Disclosed herein are methods, systems, and processes to provide coherency across disjoint caches in clustered environments. It is determined whether a data object is owned by an owner node, where the owner node is one of multiple nodes of a cluster. If the owner node for the data object is identified by the determining, a request is sent to the owner node for the data object. However, if the owner node for the data object is not identified by the determining, selects a node in the cluster is selected as the owner node, and the request for the data object is sent to the owner node.

Pseudo-first in, first out (FIFO) tag line replacement

A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

CACHE MANAGEMENT FOR SEARCH OPTIMIZATION
20230041972 · 2023-02-09 ·

A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full all cached range partitions that do not contain the data value are designated as uncached. All values that lie in the cached range partitions designated as uncached are evicted. The data value is then inserted into the target range partition, and copied to the first tier.

COMPRESSED CACHE USING DYNAMICALLY STACKED ROARING BITMAPS
20230096331 · 2023-03-30 · ·

A method for compressing data in a local cache of a web server is described. A local cache compression engine accesses values in the local cache and determines a cardinality of the values of the local cache. The local cache compression engine determines a compression rate of a compression algorithm based on the cardinality of the values of the local cache. The compression algorithm is applied to the cache based on the compression rate to generate a compressed local cache.

CACHE ARCHITECTURES FOR MEMORY DEVICES
20230100015 · 2023-03-30 ·

Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

INDICATING EXTENTS OF TRACKS IN MIRRORING QUEUES BASED ON INFORMATION GATHERED ON TRACKS IN EXTENTS IN CACHE

Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.