A method includes generating a plurality of parity blocks from a plurality of lines of data blocks. The plurality of lines of data blocks are stored in data sections of memory of a cluster of computing devices of the computing system by distributing storage of individual data blocks of the plurality of lines of data blocks among unique data sections of the cluster of computing devices. The plurality of parity blocks are stored in parity sections of memory of the cluster of computing devices by distributing storage of parity blocks of the plurality of parity blocks among unique parity sections of the cluster of computing devices.

In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.

A method of performing write operations that have been received by a data storage apparatus is provided. The method includes (a) storing page descriptors for received write operations within temporary storage, each page descriptor indicating respective data to be written; (b) upon storing each page descriptor, organizing that page descriptor into a shared working-set structure; and (c) operating a plurality of flushers to persist the data indicated by respective page descriptors to long-term persistent storage based on organization of the page descriptors in the shared working-set structure, each flusher accessing page descriptors via the shared working-set structure. An apparatus, system, and computer program product for performing a similar method are also provided.

Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

A method for asynchronous data enrichment may include receiving a query that includes a request for information about an entity. The query may specify a particular time range. In response to receiving the query, event information that is associated with the entity and that corresponds to the specified time range may be combined with additional information that is relevant to the query and that corresponds to the specified time range. The event information may initially be written to a record in an append-only data store. The additional information may become available after the event information, such that the additional information is not included in the record in the append-only data store. Instead, the additional information may initially be written to one or more additional data stores. Both the event information and the additional information may be provided in response to the query.

A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

An electronic device includes a memory controller having an improved operation speed. The memory controller includes a main memory, a processor configured to generate commands for accessing data stored in the main memory, a scheduler configured to store the commands and output the commands according to a preset criterion, a cache memory configured to cache and store data accessed by the processor among the data stored in the main memory, and a hazard filter configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduler upon receiving the write command, and provide the write command to the main memory.