Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.

Disclosed herein are methods, systems, and processes to provide coherency across disjoint caches in clustered environments. It is determined whether a data object is owned by an owner node, where the owner node is one of multiple nodes of a cluster. If the owner node for the data object is identified by the determining, a request is sent to the owner node for the data object. However, if the owner node for the data object is not identified by the determining, selects a node in the cluster is selected as the owner node, and the request for the data object is sent to the owner node.

In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

Method, apparatus and computer program product for generating filter cache are described herein. For example, the apparatus includes at least one processor and at least one non-transitory memory including program code. The at least one non-transitory memory and the program code are configured to, with the at least one processor, cause the apparatus to at least generate an index document array, generate a group identifier lookup array, generate a channel identifier lookup array, and generate a filter cache for the index document array based at least on the group identifier lookup array and the channel identifier lookup array.

Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.

A method of compressing an address includes receiving an input of a full address including a first part and a second part; checking a segment base address based on the first part in a previously stored reverse map cache (RMC); obtaining a block offset based on the segment base address and the second part; and outputting a compressed address by compressing the first part and the second part, respectively, based on the segment base address and the block offset.