Patent classifications
G06F2212/622
Processor to memory with coherency bypass
An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
HIGH PERFORMANCE INTERCONNECT
- Robert J. Safranek ,
- Robert G. Blankenship ,
- Venkatraman Iyer ,
- Jeff Willey ,
- Robert Beers ,
- Darren S. Jue ,
- Arvind A. Kumar ,
- Debendra Das Sharma ,
- Jeffrey C. Swanson ,
- Bahaa Fahim ,
- Vedaraman Geetha ,
- Aaron T. Spink ,
- Fulvio Spagna ,
- Rahul R. Shah ,
- Sitaraman V. Iyer ,
- William Harry Nale ,
- Abhishek Das ,
- Simon P. Johnson ,
- Yuvraj S. Dhillon ,
- Yen-Cheng Liu ,
- Raj K. Ramanujan ,
- Robert A. Maddox ,
- Herbert H. Hum ,
- Ashish Gupta
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
PAGE-BASED MEMORY OPERATION WITH HARDWARE INITIATED SECURE STORAGE KEY UPDATE
Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.
Efficient global cache partition and dynamic sizing for shared storage workloads
A shared cache memory can be logically partitioned among different workloads to provide isolation between workloads and avoid excessive resource contention. Each logical partition is apportioned a share of the cache memory, and is exclusive to a respective one of the workloads. Each partition has an initial size allocation. Historical data can be collected and processed for each partition and used to periodically update its size allocation.
MULTIPLE CACHE FRAMEWORK FOR MANAGING DATA FOR SCENARIO PLANNING
The embodiments disclosed herein relate to computing a transportation plan for transporting goods from one place to another across a number of shipments and that satisfy multiple shipment orders. The transportation plan may specify a transportation channel that includes one or more segments selected from service provider rate offerings that may include a means of transportation, starting location, destination location, and cost of the segment. An actionable transportation plan may be computed based on current transportation planning data. Alternative plans may be computed for a variety of scenarios in which hypothetical changes are introduced to the transportation planning data. Any combination of an actionable transportation plan and alternative plans may be computed concurrently with computations sharing a common cache of production data.
Region based split-directory scheme to adapt to large cache sizes
Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
Technologies for demoting cache lines to shared cache
Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.
EFFICIENT GLOBAL CACHE PARTITION AND DYNAMIC SIZING FOR SHARED STORAGE WORKLOADS
A shared cache memory can be logically partitioned among different workloads to provide isolation between workloads and avoid excessive resource contention. Each logical partition is apportioned a share of the cache memory, and is exclusive to a respective one of the workloads. Each partition has an initial size allocation. Historical data can be collected and processed for each partition and used to periodically update its size allocation.
APPARATUS AND METHOD FOR MANAGING STORAGE OF DATA BLOCKS
A data block storage management capability is presented. A cloud file system management capability manages storage of data blocks of a file system across multiple cloud storage services (e.g., including determining, for each data block to be stored, a storage location and a storage duration for the data block). A cloud file system management capability manages movement of data blocks of a file system between storage volumes of cloud storage services. A cloud file system management capability provides a probabilistic eviction scheme for evicting data blocks from storage volumes of cloud storage services in advance of storage deadlines by which the data blocks are to be removed from the storage volumes. A cloud file system management capability enables dynamic adaptation of the storage volume sizes of the storage volumes of the cloud storage services.
REGION BASED SPLIT-DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES
Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.