Patent classifications
G06F2212/651
Low-latency shared memory channel across address spaces in a computing system
Examples provide a method of communication between a client driver and a filesystem server. The client driver executes in a virtual machine (VM) and the filesystem server executes in a hypervisor. The method includes: allocating, by the client driver, shared memory in an address space of the VM for the communication; sending identification information for the shared memory from the client driver to the filesystem server through an inter-process communication channel between the client driver and the filesystem server; identifying, by the filesystem server in cooperation with a kernel of the hypervisor, the shared memory within an address space of the hypervisor, based on the identification information, to create a shared memory channel; sending commands from the client driver to the filesystem server through the shared memory channel; and receiving completion messages for the commands from the filesystem server to the client driver through the shared memory channel.
RESIZING NAMESPACES FOR STORAGE DEVICES
A method may include receiving, by a controller of a storage device and from a host device, a command to resize a first namespace of a plurality of namespaces stored in a non-volatile memory device of the storage device. The method may further include, relocating, by the controller, a physical block address for the non-volatile memory device from an entry in a virtual to physical table identified by a first index value to an entry in the virtual to physical table identified by a second index value, and in response to relocating the physical block address, updating, by the controller, a mapping, by a namespace table, to indicate an initial index value of a second namespace of the plurality of namespaces.
FAST DEVICE DISCOVERY FOR VIRTUAL MACHINES
A processing device of a host machine detects a read access of a memory address by a guest executing on the host machine, and causes a memory page to be provided to the guest responsive to detecting the read access. The memory address is associated with a device slot of a communication bus that is not associated with at least one hardware device, and the memory page has a page table entry, mapped to the memory address, that indicates that the memory page is a read-only memory page for the guest.
FAST RESTART OF LARGE MEMORY SYSTEMS
Utilizing a storage replica data structure includes receiving, at a hyper-kernel running on a computing node in a plurality of interconnected computing nodes, an indication of an operation pertaining to at least one of a guest physical memory address or a stable storage address. A guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on the plurality of interconnected computing nodes. It further includes updating a storage replica data structure. The storage replica data structure comprises a set of entries. The set of entries in the storage replica data structure comprises associations among guest physical memory addresses, physical memory addresses, and stable storage addresses
Burst translation look-aside buffer
A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.
INFORMATION PROCESSING APPARATUS AND CONTROL METHOD
An information processing apparatus includes a conversion buffer configured to store a conversion pair of a virtual address of a page and a physical address, a page table cache configured to store data in a page table at a level other than a last level and a physical address of the data in association with each other, a memory, and a processor coupled to the memory, and configured to store a hash of the virtual address and process management information of a conversion source in each entry of the page table cache, and when executing a maintenance instruction of deleting the conversion pair in the conversion buffer by specifying at least one of the hash of the virtual address or the process management information, delete an entry of matching at least one of the hash of the virtual address and the process management information, in the page table cache.
Virtual memory protocol segmentation offloading
Methods and systems for a more efficient transmission of network traffic are provided. According to one embodiment, presence of outbound payload data, distributed across a first and second payload buffer, within a user memory space of a network device that has been generated by a user process is determined by a bus/memory interface or a network interface unit. The payload data is fetched by performing direct virtual memory addressing of the user memory space including mapping virtual addresses of the payload buffers to corresponding physical addresses, including: (i) when the payload buffers are noncontiguous, then retrieving the outbound payload data with reference to multiple buffer descriptors having starting virtual addresses of the payload buffers and (ii) when they are contiguous, then retrieving the outbound payload data with reference to a single buffer descriptor. The outbound payload data is then segmented across one or more TCP packets.
Managing fusion of memory regions and ownership attributes for fused memory regions
A realm management unit (RMU) maintains an ownership table specifying ownership entries for corresponding memory regions defining ownership attributes specifying, from among a plurality of realms, an owner realm of the corresponding region. Each realm corresponds to at least a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the corresponding region. Memory access is controlled based on the ownership table. In response to a region fuse command specifying a fuse target address indicative contiguous regions of memory to be fused into a fused group of regions, a region fuse operation updates the ownership table to indicate that the ownership attributes for the fused group of regions are represented by a single ownership entry. This provides architectural support for enabling improvement of TLB performance.
Fast restart of large memory systems
Utilizing a storage replica data structure includes receiving, at a hyper-kernel running on a computing node in a plurality of interconnected computing nodes, an indication of an operation pertaining to at least one of a guest physical memory address or a stable storage address. A guest operating system is run on a virtual environment that is defined by a set of hyper-kernels running on the plurality of interconnected computing nodes. It further includes updating a storage replica data structure. The storage replica data structure comprises a set of entries. The set of entries in the storage replica data structure comprises associations among guest physical memory addresses, physical memory addresses, and stable storage addresses.
ADDRESS TRANSLATION
Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.