One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.

A hypervisor that allocates the computer resource of a physical computer to one or more logical partitions allocates the computer resource to be allocated to the logical partitions to the logical partitions; generates, as address conversion information, the relationship between a guest physical address and a host physical address with respect to a memory of the computer resource; enables a first address conversion portion of a processor using the address conversion information; disables the first address conversion portion after the starting of a guest OS is completed; and causes an application to be executed.

A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry, determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous, and setting a marker in the page table for indicating that the main storage pages of identified by the first PTE and second PTEs are contiguous.

According to an embodiment, an information processing apparatus includes a processing device, a first memory, and a second memory. The processing device executes first processing on first data. The second memory stores the first data and has a data access latency higher than that of the first memory. The first data includes first and second pages, the first page being read/written times not less than a threshold in a certain period shorter than a period for executing the first processing, the second page being read/written times less than the threshold in the certain period. The processing device includes a controller configured to execute first access to move the first page to the first memory and then read/write data from/to the moved first page, and execute second access to directly read/write data from/to the second page of the second memory.

A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.

A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.

A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

A microprocessor includes a translation look-aside buffer (TLB) having a plurality of TLB entries addressable by a branch address and having a branch target buffer (BTB), including a plurality of BTB entries addressable by the branch address. Each TLB entry includes a virtual address. Each BTB entry including a branch tag-way data and a target tag-way data. To perform a branch prediction, the BTB and TLB are accessed, where the TLB way associative data representing one of N sets of TLB entries is used to determine BTB hit or BTB miss. If BTB hit, the branch target address of the branch address may be obtained by accessing the TLB using target tag-way data in the BTB, or by using the branch page address when a same page bit in the hit BTB entry is set.