Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

Systems, methods and apparatus of intelligent wear-leveling with reduced write-amplification for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: storage media components; a controller configured to store data into and retrieve data from the storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized operation for wear leveling among memory cells in the data storage device. The controller is configured to perform the optimized operation for wear leveling based on the prediction.

A read-disturb-based logical storage read temperature identification system includes a global read temperature identification subsystem coupled to at least one storage device. Each at least one storage device identifies read disturb information associated with rows provided by the at least one physical block in that storage device from at least one physical block in that storage device, and maps the read disturb information associated with the rows provided by the at least one physical block in that storage device to one or more logical storage elements included in a logical-to-physical storage element mapping for that storage device to generate a local logical storage element read temperature map. Each at least one storage device may then provide its local logical storage element read temperature map to the global read temperature identification subsystem.

A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

According to one embodiment, a memory system includes a nonvolatile memory, and a controller. The controller controls the nonvolatile memory. The nonvolatile memory includes a first area where specific software is capable of being stored, and a second area where the specific software is stored. The second area has higher reliability than the first area. The controller causes the specific software to be stored in the first area when receiving a command specifying the specific software, and executes loading of the specific software stored in the first area at startup of the controller.

A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

In examples there is a computing device comprising a processor, the processor having a memory management unit. The computing device also has a memory that stores instructions that, when executed by the processor, cause the memory management unit to receive a memory access instruction comprising a virtual memory address; translate the virtual memory address to a physical memory address of the memory, and obtain permission information associated with the physical memory address. Responsive to the permission information indicating that metadata is permitted to be associated with the physical memory address, a check is made of a metadata summary table stored in the physical memory to check whether metadata is compatible with the physical memory address. Responsive to the check being unsuccessful, a trap is sent to system software of the computing device in order to trigger dynamic allocation of physical memory for storing metadata associated with the physical memory address.

Linked clone read performance (e.g., retrieving data) is improved at least by minimizing the number of input/output (I/O) operations. For a child clone, a local logical extent and an inherited logical extent are generated. The local logical extent comprises a logical block address (LBA) for data in a data region of the child clone and a physical sector address (PSA) corresponding to the LBA for the data in the data region of the child clone. The inherited logical extent spans logical extents that are accessible to the child clone. The inherited logical extent comprises an LBA for data in a data region of an ancestor of the child clone and a corresponding identifier (ID) of the ancestor. Data for an LBA in a read request may be rapidly found in the child clone (local logical extent) or an ancestor (inherited logical extent).

In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.

A node that includes data processing unit (DPU) and a processor, where the processor is configured to perform a method for utilizing a data processing unit (DPU), that includes identifying, by the DPU, a processing entity operatively connected to the DPU, receiving processing entity properties from the processing entity, storing the processing entity properties in a processing entity catalog, generating a virtual combined memory space in the processing entity catalog, and providing access to the processing entity catalog to a BIOS.