A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.

One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.

A computer-implemented method for protecting a translation lookaside buffer (TLB) from TLB pollution includes receiving, via a processor, a virtual address for a data portion, determining, via the processor, whether the virtual address has a classification of memory cache transiency, creating, via the processor, a TLB entry in a first TLB, wherein the TLB entry omits a most recently used (MRU) classification, and installing the TLB entry in a next available LRU position.

The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address. Subsequent memory referent instructions can be ordered with respect to the broadcast synchronization request by a synchronization instruction.

A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

One embodiment of a cache invalidation method includes storing an invalidation status usable by a computing node to identify, from a broadcast cache invalidation queue, a last processed invalidation that was processed with respect to an object cache used by the node. The method further comprises the node determining a set of unprocessed invalidations from the broadcast cache invalidation queue that are subsequent to the last processed invalidation determined from the invalidation status. The node processes the set of unprocessed invalidations to clear cached objects from the object cache. Based on processing the set of unprocessed invalidations to clear cached objects from the object cache, the invalidation status is updated with an identifier corresponding to a last invalidation from the set of previously unprocessed invalidations.

A method and system of managing addresses translations where in response to a request to invalidate an address translation, the scope of the address translation invalidation operation is determined; an address translation invalidation probe is installed or activated in a memory management unit (MMU) pipeline; whether an address translation undergoing a table walk operation is within a scope of the address translation invalidation probe is determined; and in response to the address translation undergoing a table walk operation being within the scope of the address translation invalidation probe, preventing or blocking the table walk operation from writing data to a translation buffer in the MMU. The probe also performs an address translation comparison to determine whether an address translation request coming down the MMU pipeline is within the scope of the probe, and if within the scope of the probe, prevents, blocks and/or rejects the address translation.

A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.

Examples described herein relate to circuitry to permit evictions of entries from a Translation Lookaside Buffer (TLB) by one or more functions or hosts and limit evictions of entries from the TLB by one or more other functions or hosts. Limiting evictions of entries from the TLB by one or more other functions or hosts can be based on a number of TLB entry evictions from the TLB over an amount of time. Limiting evictions of entries from the TLB by one or more other functions or hosts can occur by reducing a number of indices available to the one or more functions or hosts.