A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

Aspects of a storage device including a memory and a controller are provided. The controller may receive a prefetch request to retrieve data for a host having a promoted stream. The controller may access a frozen time table indicating hosts for which data has been prefetched and frozen times associated with the host and other hosts. The controller can determine whether the host has a higher priority over other hosts included in the frozen time table based on corresponding frozen times and data access parameters associated with the host. The controller may determine to prefetch the data for the host in response to the prefetch request when the host has a higher priority than the other hosts. The controller can receive a host read command associated with the promoted stream from the host and provide the prefetched data to the host in response to the host read command.

A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read/write command, checking a G2F mapping table to determine whether a required group of a L2P mapping table has been loaded to a DRAM of the flash memory controller and accordingly obtain a node index indicating which memory node of the DRAM the group is stored in; recording the node index to a first region of a SRAM of the flash memory controller; accessing the DRAM to obtain an L2P address indicating a physical address that is associated with the host read/write command from the group of the L2P mapping table by referencing the node index stored in the first region of the SRAM; and performing a read/write operation on the flash memory according to the L2P address.

A solid state drive management solution is provided, and includes: detecting that a usage status of a first storage space of an SSD meets a preset condition, where the first storage space works in a first mode; and enabling, based on the detection result, the first storage space to work in a second mode to obtain a second storage space, where a quantity of bits that can be stored in a cell in the first storage space is greater than a quantity of bits that can be stored in a cell in the second storage space.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.

Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.

A memory controller includes: a map data storage for storing map data; and a read operation controller for receiving, from a host, a read request and a target logical address corresponding to the read request, acquiring a first physical address mapped to the target logical address, based on the map data, and obtaining data stored at the first physical address. When an uncorrectable error is present in the data stored at the first physical address, the read operation controller acquires a second physical address previously mapped to the target logical address before the first physical address, obtains data stored at the second physical address, and provides the host with the data stored at the second physical address and information representing occurrence of the uncorrectable error.

A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.