A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.

According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.

The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.

A system is disclosed. The system may include a processor and a memory connected to the processor. A first storage device may be connected to the processor. The first storage device may include a first storage portion, which may include a memory page. The first storage portion may extend the memory. A second storage device may also be connected to the processor. The second storage device may also include a second storage portion. The second storage portion may also extend the memory. A load balancing daemon may migrate the memory page from the first storage portion of the first storage device to the second storage portion of the second storage device based at least in part on a first update count of the first storage device and a second update count of the second storage device.

A parser is deployed early in a machine learning pipeline to read raw data and collect useful statistics about the raw data's content to determine which items of raw data exhibit a proxy for feature importance for the machine learning model. The parser operates at high speeds that approach the disk's absolute throughput while utilizing a small memory footprint. Utilization of the parser enables the machine learning pipeline to receive a fraction of the total raw data that would otherwise be available. Several scans through the data are performed, by which proxies for feature importance are indicated and irrelevant features may be discarded and thereby not forwarded to the machine learning pipeline. This reduces the amount of memory and other hardware resources used at the server and also expedites the machine learning process.

The present technology relates to an electronic system including a host and a memory system. The host includes a request merge manager configured to generate one or more operation request sets, a first request set queue configured to store one or more of transmission request sets and operation request sets, a first scheduler configured to control the priorities of the operation request sets and the transmission request sets, a second request set queue configured to store the operation request sets sequentially output from the first request set queue, a second scheduler configured to generate a transmission request set, and a request set detector configured to transmit, to the first scheduler, request information on a request set having a highest priority.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

A multi-namespace storage device includes a nonvolatile memory which includes a first memory block and a second memory block different from the first memory block, and a memory controller which receives, from a host, a command for requesting creation of a first namespace including a first logical block number and a second namespace including a second logical page number not included in the first logical block number and receives a physical mapping command for instructing physical mapping of the first namespace. The memory controller performs a first mapping operation by mapping the first logical block number to the first memory block and performs a second mapping operation by mapping the second logical page number to a second memory page included in the second memory block in response to the physical mapping command.