Provided is a storage device including a power management integrated circuit chip; multiple non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks a state of the power during a read operation and a write operation on the non-volatile memories and, when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode regarding the read operation and the write operation on all of the non-volatile memories.

Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include writing a memory object to a first memory device of a first type of memory medium. The example method can include determining that a size of the memory object meets or exceeds a threshold data size. The example method can include writing the memory object to a second memory device that comprises a second type of memory medium different than the first type. The first memory medium can be a non-volatile memory comprising phase-change memory or resistive random access memory (RAM) and the second memory medium can be NAND Flash or NOR Flash.

A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

A storage device including: a nonvolatile memory device including a first, second and third area; and a controller to receive a first write command including a first logical block address from a host, to receive first data corresponding to the first logical block address in response to the first write command, and store the first data in the nonvolatile memory device, when the first write command includes area information, the controller stores the first data in the first area or the second area based on the area information, when the first write command does not include the area information, the controller stores the first data. in the third area, each of the first area and the second area includes memory cells each storing “n” bits (n being a positive integer), and the third area includes memory cells each storing “m” bits (m being a positive integer greater than n).

A storage device including: a nonvolatile memory device including a first, second and third area; and a controller to receive a first write command including a first logical block address from a host, to receive first data corresponding to the first logical block address in response to the first write command, and store the first data in the nonvolatile memory device, when the first write command includes area information, the controller stores the first data in the first area or the second area based on the area information, when the first write command does not include the area information, the controller stores the first data in the third area, each of the first area and the second area includes memory cells each storing “n” bits (n being a positive integer), and the third area includes memory cells each storing “m” bits (m being a positive integer greater than n).

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks. The controller controls the nonvolatile memory. The controller acquires a write amount to the nonvolatile memory in a first period. The controller calculates an estimated amount of writing to the nonvolatile memory in the first period. The controller changes, when the write amount is larger than the estimated amount by a first threshold value or more, one or more parameters used for writing of data to the nonvolatile memory.

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.