An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be stored in journals. When a journal is full, the journal can be stored to a predetermined location on the cluster block determined based on the number of entries stored by the journal, leading to a number of journals scattered throughout the cluster block at predetermined locations. Each physical chunk of media, whether written with data or marked as defective is journaled. Such a journaling scheme, where the journal locations are predetermined and each physical chunk of media is journaled is referred to as physical media-aware spatially coupled journaling. During replay the spatially coupled journals can be retrieved from the predefined locations within cluster blocks and used to rebuild the indirection mapping data structure.

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

A memory controller may control a memory device including a first storage area and a second storage area. The memory controller may include: a memory operation controller and a block information manager. The memory operation controller may control the memory device to perform a block merge operation of programming data stored in a victim block among normal blocks of the first storage area to a target block among the normal blocks, and perform a data migration operation of copying data stored in blocks of the first storage area to blocks of the second storage area. The block information manager may store block map information indicating whether each of the blocks of the first storage area is a normal block or a merge block. The target block may be changed from a normal block to a merge block by the block merge operation.

Aspects of a storage device are provided which reduce write amplification by minimizing data flushes from cache to SLC blocks during RMW operations. A memory of the storage device includes a first memory location of one or more single-level cells and a second memory location of one or more multiple-level cells. A controller of the storage device receives first data associated with a first range of logical addresses and second data associated with a second range of logical addresses. During a RMW operation of the first data, the controller determines whether the first range overlaps with the second range, and stores or flushes the second data in the first memory location when an overlap is determined. The controller stores or writes the second data in the second memory location when an overlap is not determined. Accordingly, data flushing to the single-level cells is minimized when no overlap is determined.

Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.

A data storage device includes a memory device and a controller coupled to the memory device. The memory device includes a plurality of super devices. The controller is configured to set a free space threshold value for amount of free space that each super device of the plurality of super devices can have, determine that at least one super device of the plurality of super devices is at or above the free space threshold, determine that cold zones are disposed in more than one super device of the plurality of super devices, move data from the cold zones to a first super device of the plurality of super devices wherein after moving the data, all super devices are below the free space threshold, and allocate all new super blocks among the plurality of super devices without allocating any new super blocks to the first super device.

A storage device includes a memory device including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, and a controller configured to control the memory device. The controller is configured to determine data from a host as being any one of hot data, warm data and cold data, is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to one of the destination blocks according to a degree of hotness of each piece of the unit data.

According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.