A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.

Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

A system and a method are disclosed that efficiently supports an append operation in an object storage system. A size of data received with a request for an append operation from an application is determined based on a data-alignment characteristic of a storage medium. Data that is not aligned with the data-alignment characteristic is stored in persistent memory and aggregated with other data from the application that is not aligned with the data-alignment characteristic, while data that is aligned with the data-alignment characteristic is stored directly in the storage medium. Aggregated data that becomes aligned with the data-alignment characteristic as additional requests for append operations are received are migrated to the storage medium.

According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

A storage device having enhanced operating efficiency includes a memory device with a plurality of memory blocks and a memory controller that performs an operation of de-randomizing data stored in different memory blocks using an identical random seed. The memory controller includes a random table that has a first address group including physical page addresses of a first memory block and a second address group including physical page addresses of a second memory block. The random table also has a random seed group that includes random seeds corresponding to the first address group and the second address group.

Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory in response to a command from a host. The controller manages a first area and a second area in a memory space provided to the host, to which an area of the non-volatile memory is mapped. The first area is an area used by the host as a main memory. The second area is an area where valid data is stored.

Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.