A device, method and system is directed to fast data storage on a block storage device. New data is linearly written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is linearly written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.

A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller.

[Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.

A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

A storage apparatus includes: a memory that stores data and main management information, the main management information identifying a physical address of the data; and processing circuitry configured to generate preliminary management information that includes information of the same content as the main management information, and select, as use management information, any one of the main management information and the preliminary management information upon start of the storage apparatus. Access to the data stored in the memory is performed using the selected use management information.

A device for processing commands to manage non-volatile memory includes a controller configured to obtain address information from a command, read, based on the address information, an entry of a metadata table, and determine, based on the entry of the metadata table, whether a metadata page corresponding to the address information is being processed by the controller. In response to determining that the metadata page corresponding to the address information is being processed, the controller determines a processing status of the metadata page, among a plurality of processing statuses, based on the entry of the metadata table and processes the command according to the processing status of the first metadata page. In response to determining that the metadata page corresponding to first address information is not being processed, the controller reads the metadata page from the non-volatile memory based on the entry of the metadata table.