A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.

A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.

A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

According to one embodiment, a memory system stores a part of a logical-to-physical address translation table stored in a nonvolatile memory, as a first cache, in a random-access memory, and stores a compressed logical-to-physical address translation table obtained by compressing the logical-to-physical address translation table, as a second cache, in the random-access memory. The memory system stores first information indicative of a part of a first address translation data, in a first area of a first entry of the second cache where first compressed address translation data is stored. When executing processing of checking a part of the first address translation data, the memory system refers to the first information stored in the first entry of the second cache.

A method, system and non-transitory computer readable instructions for update optimization comprising, receiving application metadata wherein the application metadata includes a likelihood of future data change metric for one or more regions of application data. Determining from the application metadata which regions of the application data have a high likelihood of data change and generating variable data chunk boundaries based on the regions of the application data that have the high likelihood of data change.

A memory controller includes a meta data memory configured to store mapping information of data stored in a plurality of memory blocks included in a memory device and valid data information indicating whether the data stored in the plurality of memory blocks is valid data, and a migration controller configured to control the memory device to perform a migration operation of moving a plurality of valid data stored in a source memory block among the plurality of memory blocks from the source memory block to a target memory block based on the mapping information and the valid data information.

The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

In an embodiment of the invention, a method comprises: requesting an update or modification on a control data in at least one flash block in a storage memory; requesting a cache memory; replicating, from the storage memory to the cache memory, the control data to be updated or to be modified; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update or modification on the control data; and moving the dirty cache link list to a for flush link list and writing an updated control data from the for flush link list to a free flash page in the storage memory.