A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

A memory controller includes a key generator, an encryption and decryption circuit, and a processor. The key generator generates a first security key and a second security key based on a write request from a host. The encryption and decryption circuit encrypts write data corresponding to the write request based on the first security key to generate encrypted write data, and encrypts the first security key based on the second security key to generate a first encrypted security key. The processor controls nonvolatile memories such that the encrypted write data, the first encrypted security key, and the second security key are programmed in at least one of the nonvolatile memories, and controls the nonvolatile memories such that a dummy program operation is performed on a page of the nonvolatile memories in which the second security key is programmed instead of erasing the encrypted write data.

A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.

A data storage device may include: a nonvolatile memory device comprising a plurality of memory blocks, each having a plurality of pages, wherein each of the pages is divided into a plurality of segments having predetermined segment offset values, and the plurality of segments are grouped into a plurality of segment groups, each comprising segments having the same segment offset value; and a controller suitable for storing data in a first segment group among the plurality of segment groups until the first segment group includes no more empty segments.

Examples described herein include a cache controller and a cache device. In some examples, the cache controller is configured, when operational, to: during processor operation, dynamically adjust a maximum number of allocated pinned regions in the cache device based on usage of pinned regions. In some examples, the cache controller is to store an entry into a tag memory based on a number of pinned entries in the cache device not being exceeded. In some examples, the entry includes meta-data information indicative of whether the data is stored in the cache device.

A memory system may include: one or more memory devices each including a plurality of memory cells for storing data; a memory for storing meta data associated with the stored data; and a memory controller in communication with the memory and the one or more memory devices and for loading the meta data from the memory, and generating first meta page based on the meta data according to a first layout, and storing the first meta page in the memory device.

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

A method for using volatile and non-volatile computer memory may comprise dividing at least a portion of the non-volatile computer memory into a plurality of bins, wherein each bin comprises a plurality of contiguous blocks of physical memory in the non-volatile memory. The method may further comprise assigning one or more processes to each of the plurality of bins, storing a process ID with metadata of a page belonging to the one or more processes, matching the page to one of the plurality of bins based on the process ID, and writing the page to a matched one of the plurality of bins.

A technique for garbage collection in a storage system includes generating regrouping metadata for one or more pages of at least two logical erase blocks (LEB). The regrouping metadata indicates an associated stream for each of the pages. Multiple of the LEBs that include valid pages associated with a first stream are selected, based on the regrouping metadata, for regrouping. The valid pages associated with the first stream from the selected LEBs are regrouped into a new LEB.

A data storage apparatus includes storage divided into unit physical regions and having data stored therein, a buffer memory having buffer memory regions loaded with a map table comprising map data respectively indicating connection information between logical addresses of a host and start physical addresses for the unit physical regions, and a controller configured to: control data input and output to and from the storage according to a request of a host, to read, based on a map table address corresponding to a logical address included in the request, the map data for the logical address from the buffer memory, and to remap the map data by merging source map data of a buffer memory region having a number of errors equal to or greater than a threshold value with victim map data of a buffer memory region having a number of errors less than the threshold value.